No instruction which can change Condition Register (CR) should be executed
after Guest CR is loaded. So the guest CR is restored after the Exit Timing in
lightweight_exit executes cmpw, which can clobber CR.
Signed-off-by: Bharat Bhushan <bharat.bhus...@freescale.com>
---
This patch is against e500mc branch.
arch/powerpc/kvm/bookehv_interrupts.S | 11 ++++++++---
1 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kvm/bookehv_interrupts.S
b/arch/powerpc/kvm/bookehv_interrupts.S
index 63fc5f0..6b9389f 100644
--- a/arch/powerpc/kvm/bookehv_interrupts.S
+++ b/arch/powerpc/kvm/bookehv_interrupts.S
@@ -574,7 +574,6 @@ lightweight_exit:
mtlr r3
mtxer r5
mtctr r6
- mtcr r7
mtsrr0 r8
mtsrr1 r9
@@ -582,14 +581,20 @@ lightweight_exit:
/* save enter time */
1:
mfspr r6, SPRN_TBRU
- mfspr r7, SPRN_TBRL
+ mfspr r9, SPRN_TBRL
mfspr r8, SPRN_TBRU
cmpw r8, r6
- PPC_STL r7, VCPU_TIMING_LAST_ENTER_TBL(r4)
+ PPC_STL r9, VCPU_TIMING_LAST_ENTER_TBL(r4)
bne 1b
PPC_STL r8, VCPU_TIMING_LAST_ENTER_TBU(r4)
#endif
+ /*
+ * Don't execute any instruction which can change CR after
+ * below instruction.
+ */
+ mtcr r7
+
/* Finish loading guest volatiles and jump to guest. */
PPC_LL r5, VCPU_GPR(r5)(r4)
PPC_LL r6, VCPU_GPR(r6)(r4)
--
1.7.0.4
--
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