Why does the cache operation need to happen on the same CPU while the L1 caches between cores are coherent?
As you know, cache operations usually operate for a range and it iterates without disabling preemption. Therefore, though you enclose the vcpu_run and handle_exit with preemption disable, the operations on a range can run on several cores. If data of address X is written from CPU0 and CPU1 executes cache flush on address X while those 2 CPUs have same TTBR, does the cache operation fail? It seems to succeed from the document from ARM that I referred before. And that's why I think the preemption disable is unnecessary. Regards Kim, Min-gyu -----Original Message----- > And you said the reason of disabling preemption as CPU-specific data such as > caches. > But as far as I know, the l1 caches are coherent. > (http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0438e/ > BABFHDFE.html) > > Can you please explain why preemption disable is necessary in detail? > if a VM tries to do a cache maintenance operation specific to that CPU that traps we want to make sure that the emulation of such operations happen on the same physical CPU to ensure correct semantics. -Christoffer -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
