On 18.07.2013, at 15:19, Bharat Bhushan wrote:
> If there is a struct page for the requested mapping then it's
> normal RAM and the mapping is set to "M" bit (coherent, cacheable)
> otherwise this is treated as I/O and we set "I + G" (cache inhibited,
> guarded)
>
> This helps setting proper TLB mapping for direct assigned device
>
> Signed-off-by: Bharat Bhushan <[email protected]>
> ---
> v2: some cleanup and added comment
> -
> arch/powerpc/kvm/e500_mmu_host.c | 23 ++++++++++++++++++-----
> 1 files changed, 18 insertions(+), 5 deletions(-)
>
> diff --git a/arch/powerpc/kvm/e500_mmu_host.c
> b/arch/powerpc/kvm/e500_mmu_host.c
> index 1c6a9d7..02eb973 100644
> --- a/arch/powerpc/kvm/e500_mmu_host.c
> +++ b/arch/powerpc/kvm/e500_mmu_host.c
> @@ -64,13 +64,26 @@ static inline u32 e500_shadow_mas3_attrib(u32 mas3, int
> usermode)
> return mas3;
> }
>
> -static inline u32 e500_shadow_mas2_attrib(u32 mas2, int usermode)
> +static inline u32 e500_shadow_mas2_attrib(u32 mas2, pfn_t pfn)
> {
> + u32 mas2_attr;
> +
> + mas2_attr = mas2 & MAS2_ATTRIB_MASK;
> +
> + /*
> + * RAM is always mappable on e500 systems, so this is identical
> + * to kvm_is_mmio_pfn(), just without its overhead.
> + */
> + if (!pfn_valid(pfn)) {
> + /* Pages not managed by Kernel are treated as I/O, set I + G */
Please also document the intermediate thought that I/O should be mapped
non-cached.
> + mas2_attr |= MAS2_I | MAS2_G;
> #ifdef CONFIG_SMP
Please separate the SMP case out of the branch.
> - return (mas2 & MAS2_ATTRIB_MASK) | MAS2_M;
> -#else
> - return mas2 & MAS2_ATTRIB_MASK;
> + } else {
> + /* Kernel managed pages are actually RAM so set "M" */
This comment doesn't tell me why M can be set ;).
Alex
> + mas2_attr |= MAS2_M;
> #endif
> + }
> + return mas2_attr;
> }
>
> /*
> @@ -313,7 +326,7 @@ static void kvmppc_e500_setup_stlbe(
> /* Force IPROT=0 for all guest mappings. */
> stlbe->mas1 = MAS1_TSIZE(tsize) | get_tlb_sts(gtlbe) | MAS1_VALID;
> stlbe->mas2 = (gvaddr & MAS2_EPN) |
> - e500_shadow_mas2_attrib(gtlbe->mas2, pr);
> + e500_shadow_mas2_attrib(gtlbe->mas2, pfn);
> stlbe->mas7_3 = ((u64)pfn << PAGE_SHIFT) |
> e500_shadow_mas3_attrib(gtlbe->mas7_3, pr);
>
> --
> 1.7.0.4
>
>
> --
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