Hi Marc,
On 06/08/2015 06:03 PM, Marc Zyngier wrote:
> As we're about to cram more information in the vgic_lr structure
> (HW interrupt number and additional state information), we switch
> to a layout similar to the HW's:
>
> - use bitfields to save space (we don't need more than 10 bits
> to represent the irq numbers)
But that will not be true for LPIs later, right? Before that I was lucky
with the irq field being 16 bits wide ;-)
So can we increase that to be at least 14 bits (8192 LPI offset + 8192
LPIs) here? The structure would still fit in 32 bits, then.
I guess guests should get away with only supporting 8K of LPIs, but if
we map hardware LPIs to guest IRQs I guess we may exceed 14 bits here.
Not sure if we could extend this further for ARM64 only, as we have more
room there and also need it only here.
Cheers,
Andre.
> - source CPU and HW interrupt can share the same field, as
> a SGI doesn't have a physical line.
>
> Signed-off-by: Marc Zyngier <marc.zyng...@arm.com>
> ---
> include/kvm/arm_vgic.h | 10 +++++++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h
> index 133ea00..4f9fa1d 100644
> --- a/include/kvm/arm_vgic.h
> +++ b/include/kvm/arm_vgic.h
> @@ -95,11 +95,15 @@ enum vgic_type {
> #define LR_STATE_ACTIVE (1 << 1)
> #define LR_STATE_MASK (3 << 0)
> #define LR_EOI_INT (1 << 2)
> +#define LR_HW (1 << 3)
>
> struct vgic_lr {
> - u16 irq;
> - u8 source;
> - u8 state;
> + unsigned irq:10;
> + union {
> + unsigned hwirq:10;
> + unsigned source:8;
> + };
> + unsigned state:4;
> };
>
> struct vgic_vmcr {
>
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