On Thu, Oct 19, 2017 at 03:57:59PM +0100, James Morse wrote: > ARM v8.2 has a feature to add implicit error synchronization barriers > whenever the CPU enters or returns from an exception level. Add code to > detect this feature and enable the SCTLR_ELx.IESB bit. > > This feature causes RAS errors that are not yet visible to software to > become pending SErrors. We expect to have firmware-first RAS support > so synchronised RAS errors will be take immediately to EL3. > Any system without firmware-first handling of errors will take the SError > either immediatly after exception return, or when we unmask SError after > entry.S's work. > > Platform level RAS support may require additional firmware support. > > Cc: Christoffer Dall <christoffer.d...@linaro.org> > Cc: Marc Zyngier <marc.zyng...@arm.com> > Signed-off-by: James Morse <james.mo...@arm.com> > Reviewed-by: Catalin Marinas <catalin.mari...@arm.com>
To be honest, I'd just set this bit unconditionally. I realise the architecture would rather we didn't do that for v8 parts where it's RES0, but we do this elsewhere (e.g. HD and HA in the TCR) and practically it's fine. Will _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
