Previously we added a dsb before reading isr_el1 to ensure that the hosts write's have finished, before we read isr_el1 to see if any of them caused an SError.
This only really matters if we have the v8.2 RAS extensions with its poison tracking and containment reporting via SError's ESR value. Before v8.2 it is very unlikely these systems will detect and report errors in a way that we can handle. Use alternatives to remove this barrier on systems without v8.2 RAS. Signed-off-by: James Morse <james.mo...@arm.com> --- Tested on A57 with v5.2-rc1, do_hvc from [0] v5.2-rc1 mean:4339 stddev:33 v5.2-rc1+patches1-5 mean:4405 stddev:31 with series 1.53% slower [0]https://git.kernel.org/pub/scm/linux/kernel/git/maz/kvm-ws-tests.git/ arch/arm64/kvm/hyp/entry.S | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/hyp/entry.S b/arch/arm64/kvm/hyp/entry.S index fa39899fe3d0..a5a4254314a1 100644 --- a/arch/arm64/kvm/hyp/entry.S +++ b/arch/arm64/kvm/hyp/entry.S @@ -17,6 +17,7 @@ #include <linux/linkage.h> +#include <asm/alternative.h> #include <asm/asm-offsets.h> #include <asm/assembler.h> #include <asm/fpsimdmacros.h> @@ -65,8 +66,11 @@ ENTRY(__guest_enter) // Now the host state is stored if we have a pending RAS SError it must // affect the host. If any asyncronous exception is pending we defer - // the guest entry. + // the guest entry. The DSB isn't necessary before v8.2 as any SError + // would be fatal. +alternative_if ARM64_HAS_RAS_EXTN dsb nshst +alternative_else_nop_endif mrs x1, isr_el1 cbz x1, 1f mov x0, #ARM_EXCEPTION_IRQ -- 2.20.1 _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
