On Fri, Feb 28, 2020 at 04:51:22PM +0000, Mark Rutland wrote:
> On Mon, Jan 27, 2020 at 11:44:28AM +0000, Andrew Murray wrote:
> > We currently expose the PMU version of the host to the guest via
> > emulation of the DFR0_EL1 and AA64DFR0_EL1 debug feature registers.
> > However many of the features offered beyond PMUv3 for 8.1 are not
> > supported in KVM. Examples of this include support for the PMMIR
> > registers (added in PMUv3 for ARMv8.4) and 64-bit event counters
> > added in (PMUv3 for ARMv8.5).
> >
> > Let's trap the Debug Feature Registers in order to limit
> > PMUVer/PerfMon in the Debug Feature Registers to PMUv3 for ARMv8.1
> > to avoid unexpected behaviour.
> >
> > Signed-off-by: Andrew Murray <andrew.mur...@arm.com>
> > ---
> > arch/arm64/include/asm/sysreg.h | 5 +++++
> > arch/arm64/kvm/sys_regs.c | 11 +++++++++++
> > 2 files changed, 16 insertions(+)
> >
> > diff --git a/arch/arm64/include/asm/sysreg.h
> > b/arch/arm64/include/asm/sysreg.h
> > index 6e919fa..1009878 100644
> > --- a/arch/arm64/include/asm/sysreg.h
> > +++ b/arch/arm64/include/asm/sysreg.h
> > @@ -672,6 +672,11 @@
> > #define ID_AA64DFR0_TRACEVER_SHIFT 4
> > #define ID_AA64DFR0_DEBUGVER_SHIFT 0
> >
> > +#define ID_DFR0_PERFMON_SHIFT 24
> > +
> > +#define ID_DFR0_EL1_PMUVER_8_1 4
> > +#define ID_AA64DFR0_EL1_PMUVER_8_1 4
> > +
> > #define ID_ISAR5_RDM_SHIFT 24
> > #define ID_ISAR5_CRC32_SHIFT 16
> > #define ID_ISAR5_SHA2_SHIFT 12
> > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> > index 9f21659..3f0f3cc 100644
> > --- a/arch/arm64/kvm/sys_regs.c
> > +++ b/arch/arm64/kvm/sys_regs.c
> > @@ -1085,6 +1085,17 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu,
> > (0xfUL << ID_AA64ISAR1_API_SHIFT) |
> > (0xfUL << ID_AA64ISAR1_GPA_SHIFT) |
> > (0xfUL << ID_AA64ISAR1_GPI_SHIFT));
> > + } else if (id == SYS_ID_AA64DFR0_EL1) {
> > + /* Limit guests to PMUv3 for ARMv8.1 */
> > + val = cpuid_feature_cap_signed_field_width(val,
> > + ID_AA64DFR0_PMUVER_SHIFT,
> > + 4, ID_AA64DFR0_EL1_PMUVER_8_1);
> > + } else if (id == SYS_ID_DFR0_EL1) {
> > + /* Limit guests to PMUv3 for ARMv8.1 */
> > + val = cpuid_feature_cap_signed_field_width(val,
> > + ID_DFR0_PERFMON_SHIFT,
> > + 4, ID_DFR0_EL1_PMUVER_8_1);
> > +
>
> Unfortunately, ID_AA64DFR0_EL1.PMUVer and ID_DFR0_EL1.PerfMon don't
> follow the usual ID scheme, and cannot be treated as signed fields.
>
> Per ARM DDI 0487E.a, page D13-2825, they follow an alternative scheme
> that is treated as unsigned, with 0xF additionally being treated as an
> architected PMU version not being implemented. For KVM we'll want to
> convert 0xF to 0x0.
>
> I'll respin these patches accordingly.
I've pushed an updated series to:
https://git.kernel.org/pub/scm/linux/kernel/git/mark/linux.git/log/?h=arm64/pmu-8.5
Hopefully I'll get the chance to give that a go on ARMv8.{0,1} hardware
on Monday. I'm not sure how useful the PMU in FVPs is these days, so I'm
not sure how far I can test the ARMv8.5+ bits.
Thanks,
Mark.
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
