check_pmcr() checks the IMP field is different than 0.
However A zero IMP field is permitted by the architecture,
meaning the MIDR_EL1 should be looked at instead. This
causes TCG to fail this test on '-cpu max' because in
that case PMCR.IMP is set equal to MIDR_EL1.Implementer
which is 0.
So let's remove the check_pmcr() test and just print PMCR
info in the pmu_probe() function.
Signed-off-by: Eric Auger <eric.au...@redhat.com>
Reported-by: Peter Maydell <peter.mayd...@linaro.org>
---
arm/pmu.c | 39 ++++++++++++++-------------------------
1 file changed, 14 insertions(+), 25 deletions(-)
diff --git a/arm/pmu.c b/arm/pmu.c
index 0122f0a..44f3543 100644
--- a/arm/pmu.c
+++ b/arm/pmu.c
@@ -134,29 +134,6 @@ static inline void precise_instrs_loop(int loop, uint32_t
pmcr)
}
#endif
-/*
- * As a simple sanity check on the PMCR_EL0, ensure the implementer field isn't
- * null. Also print out a couple other interesting fields for diagnostic
- * purposes. For example, as of fall 2016, QEMU TCG mode doesn't implement
- * event counters and therefore reports zero event counters, but hopefully
- * support for at least the instructions event will be added in the future and
- * the reported number of event counters will become nonzero.
- */
-static bool check_pmcr(void)
-{
- uint32_t pmcr;
-
- pmcr = get_pmcr();
-
- report_info("PMU implementer/ID code/counters: %#x(\"%c\")/%#x/%d",
- (pmcr >> PMU_PMCR_IMP_SHIFT) & PMU_PMCR_IMP_MASK,
- ((pmcr >> PMU_PMCR_IMP_SHIFT) & PMU_PMCR_IMP_MASK) ? : ' ',
- (pmcr >> PMU_PMCR_ID_SHIFT) & PMU_PMCR_ID_MASK,
- (pmcr >> PMU_PMCR_N_SHIFT) & PMU_PMCR_N_MASK);
-
- return ((pmcr >> PMU_PMCR_IMP_SHIFT) & PMU_PMCR_IMP_MASK) != 0;
-}
-
/*
* Ensure that the cycle counter progresses between back-to-back reads.
*/
@@ -278,9 +255,22 @@ static void pmccntr64_test(void)
/* Return FALSE if no PMU found, otherwise return TRUE */
static bool pmu_probe(void)
{
+ uint32_t pmcr;
+
pmu_version = get_pmu_version();
+ if (pmu_version == 0 || pmu_version == 0xf)
+ return false;
+
report_info("PMU version: %d", pmu_version);
- return pmu_version != 0 && pmu_version != 0xf;
+
+ pmcr = get_pmcr();
+ report_info("PMU implementer/ID code/counters: %#x(\"%c\")/%#x/%d",
+ (pmcr >> PMU_PMCR_IMP_SHIFT) & PMU_PMCR_IMP_MASK,
+ ((pmcr >> PMU_PMCR_IMP_SHIFT) & PMU_PMCR_IMP_MASK) ? : ' ',
+ (pmcr >> PMU_PMCR_ID_SHIFT) & PMU_PMCR_ID_MASK,
+ (pmcr >> PMU_PMCR_N_SHIFT) & PMU_PMCR_N_MASK);
+
+ return true;
}
int main(int argc, char *argv[])
@@ -301,7 +291,6 @@ int main(int argc, char *argv[])
report_prefix_push(argv[1]);
if (argc > 2)
cpi = atol(argv[2]);
- report(check_pmcr(), "Control register");
report(check_cycles_increase(),
"Monotonically increasing cycle count");
report(check_cpi(cpi), "Cycle/instruction ratio");
--
2.20.1
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