These are remaining patches from V4 series which had some pending reviews from Suzuki (https://patchwork.kernel.org/cover/11557333/). Also dropped [PATCH 15/17] as that will need some more investigation and rework.
This series applies on 5.8-rc3. Cc: Catalin Marinas <catalin.mari...@arm.com> Cc: Will Deacon <w...@kernel.org> Cc: Mark Rutland <mark.rutl...@arm.com> Cc: Marc Zyngier <m...@kernel.org> Cc: James Morse <james.mo...@arm.com> Cc: Suzuki K Poulose <suzuki.poul...@arm.com> Cc: kvmarm@lists.cs.columbia.edu Cc: linux-arm-ker...@lists.infradead.org Cc: linux-ker...@vger.kernel.org Changes in V5: (https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=293885) - Dropped TGRAN features along with it's macros from ID_AA64MMFR0 per Suzuki - Replaced with FTR_HIGHER_SAFE for SpecSEI feature in ID_AA64MMFR1 per Suzuki - Dropped patch "arm64/cpufeature: Add remaining feature bits in ID_AA64DFR0 register" Changes in V4: (https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=290085) - Updated ftr_id_dfr0[] with a documentation for now missing [31:28] Tracfilt per Will - Fixed erroneous bit width value from 28 to 4 for double lock feature per Will - Replaced ID_SANITIZED() with ID_HIDDEN() for SYS_ID_DFR1_EL1 per Suzuki - Fixed positions for register definitions as per new name based grouping per Will - Replaced FTR_VISIBLE with FTR_HIDDEN for TLB feature in ID_AA64ISAR0 per Suzuki - Replaced FTR_VISIBLE with FTR_HIDDEN for MPAM and SEL2 in ID_AA64PFR0 per Suzuki - Replaced FTR_VISIBLE with FTR_HIDDEN for MPAMFRAC and RASFRAC in ID_AA64PFR1 per Suzuki - Dropped both MTE and BT features from ftr_id_aa64pfr1[] to be added later per Suzuki - Added ID_MMFR4_EL1 into the cpuinfo_arm64 context per Will Changes in V3: (https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=281211) - Rebased on git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git (for-next/cpufeature) Changes in V2: (https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=270605) - Added Suggested-by tag from Mark Rutland for all changes he had proposed - Added comment for SpecSEI feature on why it is HIGHER_SAFE per Suzuki - Added a patch which makes ID_AA64DFR0_DOUBLELOCK a signed feature per Suzuki - Added ID_DFR1 and ID_MMFR5 system register definitions per Will - Added remaining features bits for relevant 64 bit system registers per Will - Changed commit message on [PATCH 5/7] regarding TraceFilt feature per Suzuki - Changed ID_PFR2.CSV3 (FTR_STRICT -> FTR_NONSTRICT) as 64 bit registers per Will - Changed ID_PFR0.CSV2 (FTR_STRICT -> FTR_NONSTRICT) as 64 bit registers per Will - Changed some commit messages Changes in V1: (https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=234093) Anshuman Khandual (4): arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR0 register arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR1 register arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR2 register arm64/cpufeature: Replace all open bits shift encodings with macros arch/arm64/include/asm/sysreg.h | 42 +++++++++++++++++++++ arch/arm64/kernel/cpufeature.c | 67 ++++++++++++++++++++------------- 2 files changed, 83 insertions(+), 26 deletions(-) -- 2.20.1 _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
