[PATCH v5 1/7] arm64: Allow the definition of UNKNOWN system register fields

[Akihiko Odaki]

From: Marc Zyngier <m...@kernel.org>

The CCSIDR_EL1 register contains an UNKNOWN field (which replaces
fields that were actually defined in previous revisions of the
architecture).

Define an 'Unkn' field type modeled after the Res0/Res1 types
to allow such description. This allows the generation of

  #define CCSIDR_EL1_UNKN     (UL(0) | GENMASK_ULL(31, 28))

which may have its use one day. Hopefully the architecture doesn't
add too many of those in the future.

Signed-off-by: Marc Zyngier <m...@kernel.org>
Signed-off-by: Akihiko Odaki <akihiko.od...@gmail.com>
Reviewed-by: Mark Brown <broo...@kernel.org>
---
 arch/arm64/tools/gen-sysreg.awk | 20 +++++++++++++++++++-
 arch/arm64/tools/sysreg         |  2 ++
 2 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/tools/gen-sysreg.awk b/arch/arm64/tools/gen-sysreg.awk
index db461921d256..f6909a6b8380 100755
--- a/arch/arm64/tools/gen-sysreg.awk
+++ b/arch/arm64/tools/gen-sysreg.awk
@@ -98,6 +98,7 @@ END {
 
        res0 = "UL(0)"
        res1 = "UL(0)"
+       unkn = "UL(0)"
 
        next_bit = 63
 
@@ -112,11 +113,13 @@ END {
 
        define(reg "_RES0", "(" res0 ")")
        define(reg "_RES1", "(" res1 ")")
+       define(reg "_UNKN", "(" unkn ")")
        print ""
 
        reg = null
        res0 = null
        res1 = null
+       unkn = null
 
        next
 }
@@ -134,6 +137,7 @@ END {
 
        res0 = "UL(0)"
        res1 = "UL(0)"
+       unkn = "UL(0)"
 
        define("REG_" reg, "S" op0 "_" op1 "_C" crn "_C" crm "_" op2)
        define("SYS_" reg, "sys_reg(" op0 ", " op1 ", " crn ", " crm ", " op2 
")")
@@ -161,7 +165,9 @@ END {
                define(reg "_RES0", "(" res0 ")")
        if (res1 != null)
                define(reg "_RES1", "(" res1 ")")
-       if (res0 != null || res1 != null)
+       if (unkn != null)
+               define(reg "_UNKN", "(" unkn ")")
+       if (res0 != null || res1 != null || unkn != null)
                print ""
 
        reg = null
@@ -172,6 +178,7 @@ END {
        op2 = null
        res0 = null
        res1 = null
+       unkn = null
 
        next
 }
@@ -190,6 +197,7 @@ END {
         next_bit = 0
        res0 = null
        res1 = null
+       unkn = null
 
        next
 }
@@ -215,6 +223,16 @@ END {
        next
 }
 
+/^Unkn/ && (block == "Sysreg" || block == "SysregFields") {
+       expect_fields(2)
+       parse_bitdef(reg, "UNKN", $2)
+       field = "UNKN_" msb "_" lsb
+
+       unkn = unkn " | GENMASK_ULL(" msb ", " lsb ")"
+
+       next
+}
+
 /^Field/ && (block == "Sysreg" || block == "SysregFields") {
        expect_fields(3)
        field = $3
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 384757a7eda9..8f26fe1bedc6 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -15,6 +15,8 @@
 
 # Res1 <msb>[:<lsb>]
 
+# Unkn <msb>[:<lsb>]
+
 # Field        <msb>[:<lsb>]   <name>
 
 # Enum <msb>[:<lsb>]   <name>
-- 
2.38.1

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