J?rgen Keil wrote:
>I also noticed that in the non-working slot case (pcic
>instance 1) no "{mem,I/O} {Base,Lim} 0" is reported:
>
>pciclass,0607001: BAR0 = [0xdf000]
>pciclass,0607001: mem Base 0 = [0x0] <<<<<<<<<<<<
>pciclass,0607001: mem Lim 0 = [0x0] <<<<<<<<<<<<
>pciclass,0607001: mem Base 1 = [0x0]
>pciclass,0607001: mem Lim 1 = [0x0]
>pciclass,0607001: I/0 Base 0 = [0x0] <<<<<<<<<<<<
>pciclass,0607001: I/O Lim 0 = [0x0] <<<<<<<<<<<<
>pciclass,0607001: I/O Base 1 = [0x0]
>pciclass,0607001: I/O Lim 1 = [0x0]
>
>
>
This can happen if the cardbus driver receives an insertion interrupt
but finds no children. The mem range and io range are calculated by
summing up the resource requirement of the children.
If no children, then no resource is assigned.
We can verify this by setting a breakpointn in cardbus_probe_children()
and check its return value to see if a child is detected.
cardbus_probe_children() is called repeatedly probing every dev/func on
the bus.
Suppose you only inserted one card, then the bus number should be 3. And
the PC Card inserted is supposed to be 3(bus), 0(dev), 0(func).
We may also set cardbus_debug as 9, then /var/adm/messages should show
the probing process. Check the result of probing 3,0,0.
With the card inserted, run some PCI scanning tools like lspci or
scanpci, if 3,0,0 isn't found, then the device may not be connected
properly (or powered-on properly) ?
Is the card powered on?
>The working slot (pcic instance 0) reports:
>
>pciclass,0607000: BAR0 = [0xde000]
>pciclass,0607000: mem Base 0 = [0xd0002000] <<<<<<<<<<<<
>pciclass,0607000: mem Lim 0 = [0xd0002000] <<<<<<<<<<<<
>pciclass,0607000: mem Base 1 = [0x0]
>pciclass,0607000: mem Lim 1 = [0x0]
>pciclass,0607000: I/0 Base 0 = [0xb000] <<<<<<<<<<<<
>pciclass,0607000: I/O Lim 0 = [0xb07c] <<<<<<<<<<<<
>pciclass,0607000: I/O Base 1 = [0x0]
>pciclass,0607000: I/O Lim 1 = [0x0]
>
>Another difference between pcic#0 and pcic#1 is the contents of
>pci registers "SYS CTL 0x80" and "Card CTL 0x91".
>
>Is that a problem, that pcic#1 reports no addresses for mem and
>I/O 0 ??
>
>
SYS CTL and Card CTL are vendor dependent. Yours is an ENE controller. I
don't know if it's 100% compatible with TI.
The difference is on bit0 for Card CTL(0x91) and on bit13 for SYS CTL(0x80).
On a TI cardbus controller, these are status bits, should not matter.
Vincent.
