Andrew Brunner schrieb:
This is relatively new theory which required low-level CPU code to perform such locks.
This is not new. String operations (CMPS...) can be interrupted since a long time, and it took some more time until even the single-core CPUs could resume such an interrupted instruction correctly.
You're right that CMPXCHG and similar instructions have been missing in older instruction sets, but these would have been useful also in single-core CPUs with interrupt capabilities. Really new is the need for cache synchronization, when multiple processors or cores use their own caches, including on-chip (instruction...) caches. But wasn't this already of concern in memory-mapped I/O (graphics cards)? Cache "look aside"?
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