Lukasz Sokol wrote:
On 09/02/2012 11:18, Mark Morgan Lloyd wrote:
Lukasz Sokol wrote:
On 09/02/2012 10:01, Sven Barth wrote:
The memory that is used by CPU caches is the fastest (but also
the most expensive that's why it's only used for the relatively
small caches).
Regards, Sven
Is there a way for a non-kernel-developer or plain FPC/Laz user to
control what is stored in cpu cache ? I thought cache management is
done transparently to userspace...?
Only on IA-64 ("Itanic") as far as I know, and in any case for
prefetches etc. to be effective the application code would have to be
intimately familiar with the details of the hardware implementation.
It's the sort of thing that would be a compile-time option on a Cray
:-)
Thought so ;) (disclaimer : I read lkml sometimes stumbling upon devs
reordering paddings in structures to make them fit into cachelines)
Which is a special case, since the kernel will have a fairly good idea
of the platform's capabilities.
The first system I came across with a cache was one of these
http://www.picklesnet.com/burroughs/images/fullsize/burr0116.jpg circa
1980. These days I've got things like Suns around the place, and it's
pretty certain that any assumptions made about x86 cache architecture
wouldn't apply to those since not only will line length etc. differ but
so will the relative speeds of the connection between CPU and cache
compared with cache and main memory.
--
Mark Morgan Lloyd
markMLl .AT. telemetry.co .DOT. uk
[Opinions above are the author's, not those of his employers or colleagues]
--
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