Matt wrote > I set SDA as an input in order to read > the (N)ACK from the slave but the FT4232 does not stop driving the SDA > line until half way through the clock cycle...
AFAIK, this is expected behavior. When in three-phase clock mode, the FTDI chip will hold the data pin high (assuming that the transmitted data bit was a 1 of course) until after the clock line has gone low in order to ensure that data is available on the falling edge of the clock. The same thing is done on the rising edge, obviously. Matt wrote > This could easily be interpreted by other slave > devices as a start condition and would interfere with their hw driven > state machines. If I understand the problem correctly, your I2C slave device is attempting to drive the data line low before the clock has fully transitioned to a low state. If this is the case, then I would say that you would have this problem no matter what the FTDI chip did (if anything, the FTDI chip attempting to keep the data line high would possibly prevent other chips on the bus from seeing a start condition). As for clock stretching, no, I am not aware of a command or explicit support for clock stretching (someone correct me if I am wrong here...). You could always send one bit/byte at a time through MPSSE and check the clock manually before each transmission, but that is essentially bit banging like you are doing now. -- View this message in context: http://libftdi.141977.n3.nabble.com/Driving-open-collector-in-mpsse-mode-i2c-woes-tp3647284p3658349.html Sent from the libFTDI mailing list archive at Nabble.com. -- libftdi - see http://www.intra2net.com/en/developer/libftdi for details. To unsubscribe send a mail to [email protected]
