Signed-off-by: Paul Moore <[email protected]>
---
tests/11-basic-basic_errors.py | 4 ++--
tests/15-basic-resolver.py | 8 ++++----
tests/16-sim-arch_basic.py | 12 ++++++------
tests/17-sim-arch_merge.py | 8 ++++----
tests/19-sim-missing_syscalls.py | 4 ++--
tests/23-sim-arch_all_le_basic.c | 10 +++++-----
tests/23-sim-arch_all_le_basic.py | 12 ++++++------
tests/26-sim-arch_all_be_basic.c | 2 +-
tests/26-sim-arch_all_be_basic.py | 4 ++--
9 files changed, 32 insertions(+), 32 deletions(-)
diff --git a/tests/11-basic-basic_errors.py b/tests/11-basic-basic_errors.py
index 5f5eccf..10e5d7d 100755
--- a/tests/11-basic-basic_errors.py
+++ b/tests/11-basic-basic_errors.py
@@ -74,8 +74,8 @@ def test():
pass
f = SyscallFilter(ALLOW)
- f.remove_arch(Arch.NATIVE)
- f.add_arch(Arch.X86)
+ f.remove_arch(Arch())
+ f.add_arch(Arch("x86"))
try:
f.add_rule_exactly(KILL, "socket", Arg(0, EQ, 2))
except RuntimeError:
diff --git a/tests/15-basic-resolver.py b/tests/15-basic-resolver.py
index a724d1b..6009d6d 100755
--- a/tests/15-basic-resolver.py
+++ b/tests/15-basic-resolver.py
@@ -39,12 +39,12 @@ def test():
except RuntimeError:
pass
- sys_num = resolve_syscall(Arch.NATIVE, "open")
- sys_name = resolve_syscall(Arch.NATIVE, sys_num)
+ sys_num = resolve_syscall(Arch(), "open")
+ sys_name = resolve_syscall(Arch(), sys_num)
if (sys_name != "open"):
raise RuntimeError("Test failure")
- sys_num = resolve_syscall(Arch.NATIVE, "socket")
- sys_name = resolve_syscall(Arch.NATIVE, sys_num)
+ sys_num = resolve_syscall(Arch(), "socket")
+ sys_name = resolve_syscall(Arch(), sys_num)
if (sys_name != "socket"):
raise RuntimeError("Test failure")
diff --git a/tests/16-sim-arch_basic.py b/tests/16-sim-arch_basic.py
index b067d1b..e2020e3 100755
--- a/tests/16-sim-arch_basic.py
+++ b/tests/16-sim-arch_basic.py
@@ -30,12 +30,12 @@ from seccomp import *
def test(args):
f = SyscallFilter(KILL)
- f.remove_arch(Arch.NATIVE)
- f.add_arch(Arch.X86)
- f.add_arch(Arch.X86_64)
- f.add_arch(Arch.X32)
- f.add_arch(Arch.ARM)
- f.add_arch(Arch.MIPSEL)
+ f.remove_arch(Arch())
+ f.add_arch(Arch("x86"))
+ f.add_arch(Arch("x86_64"))
+ f.add_arch(Arch("x32"))
+ f.add_arch(Arch("arm"))
+ f.add_arch(Arch("mipsel"))
f.add_rule(ALLOW, "read", Arg(0, EQ, sys.stdin.fileno()))
f.add_rule(ALLOW, "write", Arg(0, EQ, sys.stdout.fileno()))
f.add_rule(ALLOW, "write", Arg(0, EQ, sys.stderr.fileno()))
diff --git a/tests/17-sim-arch_merge.py b/tests/17-sim-arch_merge.py
index 84cf840..970cc4c 100755
--- a/tests/17-sim-arch_merge.py
+++ b/tests/17-sim-arch_merge.py
@@ -31,10 +31,10 @@ from seccomp import *
def test(args):
f32 = SyscallFilter(KILL)
f64 = SyscallFilter(KILL)
- f32.remove_arch(Arch.NATIVE)
- f64.remove_arch(Arch.NATIVE)
- f32.add_arch(Arch.X86)
- f64.add_arch(Arch.X86_64)
+ f32.remove_arch(Arch())
+ f64.remove_arch(Arch())
+ f32.add_arch(Arch("x86"))
+ f64.add_arch(Arch("x86_64"))
f32.add_rule(ALLOW, "read", Arg(0, EQ, sys.stdin.fileno()))
f32.add_rule(ALLOW, "write", Arg(0, EQ, sys.stdout.fileno()))
f32.add_rule(ALLOW, "write", Arg(0, EQ, sys.stderr.fileno()))
diff --git a/tests/19-sim-missing_syscalls.py b/tests/19-sim-missing_syscalls.py
index 7c6d2f2..2762c43 100755
--- a/tests/19-sim-missing_syscalls.py
+++ b/tests/19-sim-missing_syscalls.py
@@ -30,8 +30,8 @@ from seccomp import *
def test(args):
f = SyscallFilter(KILL)
- f.remove_arch(Arch.NATIVE)
- f.add_arch(Arch.X86)
+ f.remove_arch(Arch())
+ f.add_arch(Arch("x86"))
f.add_rule(ALLOW, "tuxcall")
try:
f.add_rule_exactly(ALLOW, "tuxcall")
diff --git a/tests/23-sim-arch_all_le_basic.c b/tests/23-sim-arch_all_le_basic.c
index 446a8d8..1035d1d 100644
--- a/tests/23-sim-arch_all_le_basic.c
+++ b/tests/23-sim-arch_all_le_basic.c
@@ -44,19 +44,19 @@ int main(int argc, char *argv[])
if (rc != 0)
goto out;
- rc = seccomp_arch_add(ctx, SCMP_ARCH_X86);
+ rc = seccomp_arch_add(ctx, seccomp_arch_resolve_name("x86"));
if (rc != 0)
goto out;
- rc = seccomp_arch_add(ctx, SCMP_ARCH_X86_64);
+ rc = seccomp_arch_add(ctx, seccomp_arch_resolve_name("x86_64"));
if (rc != 0)
goto out;
- rc = seccomp_arch_add(ctx, SCMP_ARCH_X32);
+ rc = seccomp_arch_add(ctx, seccomp_arch_resolve_name("x32"));
if (rc != 0)
goto out;
- rc = seccomp_arch_add(ctx, SCMP_ARCH_ARM);
+ rc = seccomp_arch_add(ctx, seccomp_arch_resolve_name("arm"));
if (rc != 0)
goto out;
- rc = seccomp_arch_add(ctx, SCMP_ARCH_MIPSEL);
+ rc = seccomp_arch_add(ctx, seccomp_arch_resolve_name("mipsel"));
if (rc != 0)
goto out;
diff --git a/tests/23-sim-arch_all_le_basic.py
b/tests/23-sim-arch_all_le_basic.py
index a126e7e..ba794ae 100755
--- a/tests/23-sim-arch_all_le_basic.py
+++ b/tests/23-sim-arch_all_le_basic.py
@@ -30,12 +30,12 @@ from seccomp import *
def test(args):
f = SyscallFilter(KILL)
- f.remove_arch(Arch.NATIVE)
- f.add_arch(Arch.X86)
- f.add_arch(Arch.X86_64)
- f.add_arch(Arch.X32)
- f.add_arch(Arch.ARM)
- f.add_arch(Arch.MIPSEL)
+ f.remove_arch(Arch())
+ f.add_arch(Arch("x86"))
+ f.add_arch(Arch("x86_64"))
+ f.add_arch(Arch("x32"))
+ f.add_arch(Arch("arm"))
+ f.add_arch(Arch("mipsel"))
f.add_rule(ALLOW, "read", Arg(0, EQ, sys.stdin.fileno()))
f.add_rule(ALLOW, "write", Arg(0, EQ, sys.stdout.fileno()))
f.add_rule(ALLOW, "write", Arg(0, EQ, sys.stderr.fileno()))
diff --git a/tests/26-sim-arch_all_be_basic.c b/tests/26-sim-arch_all_be_basic.c
index be892fb..251dcf7 100644
--- a/tests/26-sim-arch_all_be_basic.c
+++ b/tests/26-sim-arch_all_be_basic.c
@@ -43,7 +43,7 @@ int main(int argc, char *argv[])
if (rc != 0)
goto out;
- rc = seccomp_arch_add(ctx, SCMP_ARCH_MIPS);
+ rc = seccomp_arch_add(ctx, seccomp_arch_resolve_name("mips"));
if (rc != 0)
goto out;
diff --git a/tests/26-sim-arch_all_be_basic.py
b/tests/26-sim-arch_all_be_basic.py
index e8870d3..4c78252 100755
--- a/tests/26-sim-arch_all_be_basic.py
+++ b/tests/26-sim-arch_all_be_basic.py
@@ -29,8 +29,8 @@ from seccomp import *
def test(args):
f = SyscallFilter(KILL)
- f.remove_arch(Arch.NATIVE)
- f.add_arch(Arch.MIPS)
+ f.remove_arch(Arch())
+ f.add_arch(Arch("mips"))
f.add_rule(ALLOW, "read", Arg(0, EQ, sys.stdin.fileno()))
f.add_rule(ALLOW, "write", Arg(0, EQ, sys.stdout.fileno()))
f.add_rule(ALLOW, "write", Arg(0, EQ, sys.stderr.fileno()))
------------------------------------------------------------------------------
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