Hi all,
Now both qemu and kvm support 5-level paging.
We can start qemu with a "cpu,+la57" to set 57-bit vitrual address space.
So VM can be aware that it need to enable 5-level paging.
We can also set another "cpu,phys-bits=52" to set the VM physical
address space.
Actually, VM can still turn on 5 level paging even without
"phys-bits=52", yet this means
the guest physical address width are limited, meaning less practical
benefits.
In to support 5-level paging, I suggest to add two attribute for the
domain cpu element in libvirt.
<cpu la57='yes', phys-bits='52'\>
Here we need to be able to set phys-bits directly, because it is
potentially migration sensitive.
If la57='no', libvirt will ignore phys-bits, no matter whether hardware
support la57.
If la57='yes', libvirt will probe the host capability, and will throw
error if hardware does support la57.
If la57='yes', even phys-bits less than 52, libvirt will also pass it
to qemu though less practical benefits.
[info]
[1] [Qemu-devel] [PATCH]x86: implement la57 paging mode
<https://lists.gnu.org/archive/html/qemu-devel/2016-12/msg02096.html>
[2] [Qemu-devel] [PATCH v4 2/5] x86: Allow physical address bits to be
set <https://lists.gnu.org/archive/html/qemu-devel/2016-07/msg01950.html>
BR
Shaohe Feng
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