From: Bing Niu <bing....@intel.com>
If we have some membw_info data, then we need to calculate the number
of MBA controllers on the system. The value cannot be obtained from a
direct query to the RDT kernel module, but it is the same as the last
level cache value which is calculated by traversing the cache hierarchy
of host(/sys/bus/cpu/devices/cpuX/cache/).
Signed-off-by: Bing Niu <bing....@intel.com>
Reviewed-by: John Ferlan <jfer...@redhat.com>
---
src/util/virresctrl.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/src/util/virresctrl.c b/src/util/virresctrl.c
index b12a05c..f454868 100644
--- a/src/util/virresctrl.c
+++ b/src/util/virresctrl.c
@@ -608,6 +608,20 @@ virResctrlInfoGetCache(virResctrlInfoPtr resctrl,
if (virResctrlInfoIsEmpty(resctrl))
return 0;
+ /* Let's take the opportunity to update the number of last level
+ * cache. This number of memory bandwidth controller is same with
+ * last level cache */
+ if (resctrl->membw_info) {
+ virResctrlInfoMemBWPtr membw_info = resctrl->membw_info;
+
+ if (level > membw_info->last_level_cache) {
+ membw_info->last_level_cache = level;
+ membw_info->max_id = 0;
+ } else if (membw_info->last_level_cache == level) {
+ membw_info->max_id++;
+ }
+ }
+
if (level >= resctrl->nlevels)
return 0;
--
2.7.4
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