Samsung's ARM Cortex-A15 based SoCs are known as Exynos5 series of
SoCs. This patch adds the support for Exynos5.

Signed-off-by: Chander Kashyap <chander.kash...@linaro.org>
---
Changes for v2:
        - This patch was part of "EXYNOS: Add SMDK5250 board support"
        - Now it is seprated as SoC support.
Changes for v3:
        - Populated complete exynos5 gpio structures
Changes for v4:
        - Added dmc.h and tzpc.h header files
        - Renamed EXYNOS5_PHY*_CTRL_BASE to EXYNOS5_DMC_PHY*_BASE
Changes for v5:
        - None
Changes for v5:
        - None

 arch/arm/cpu/armv7/exynos/clock.c        |  208 +++++++++++++++++++-
 arch/arm/include/asm/arch-exynos/clock.h |  326 ++++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-exynos/cpu.h   |   35 +++-
 arch/arm/include/asm/arch-exynos/dmc.h   |  146 +++++++++++++
 arch/arm/include/asm/arch-exynos/gpio.h  |   99 +++++++++-
 arch/arm/include/asm/arch-exynos/tzpc.h  |   52 +++++
 6 files changed, 854 insertions(+), 12 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-exynos/dmc.h
 create mode 100644 arch/arm/include/asm/arch-exynos/tzpc.h

diff --git a/arch/arm/cpu/armv7/exynos/clock.c 
b/arch/arm/cpu/armv7/exynos/clock.c
index 4d92c53..2f7048b 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -92,6 +92,72 @@ static unsigned long exynos4_get_pll_clk(int pllreg)
        return fout;
 }
 
+/* exynos5: return pll clock frequency */
+static unsigned long exynos5_get_pll_clk(int pllreg)
+{
+       struct exynos5_clock *clk =
+               (struct exynos5_clock *)samsung_get_base_clock();
+       unsigned long r, m, p, s, k = 0, mask, fout;
+       unsigned int freq;
+
+       switch (pllreg) {
+       case APLL:
+               r = readl(&clk->apll_con0);
+               break;
+       case MPLL:
+               r = readl(&clk->mpll_con0);
+               break;
+       case EPLL:
+               r = readl(&clk->epll_con0);
+               k = readl(&clk->epll_con1);
+               break;
+       case VPLL:
+               r = readl(&clk->vpll_con0);
+               k = readl(&clk->vpll_con1);
+               break;
+       default:
+               printf("Unsupported PLL (%d)\n", pllreg);
+               return 0;
+       }
+
+       /*
+        * APLL_CON: MIDV [25:16]
+        * MPLL_CON: MIDV [25:16]
+        * EPLL_CON: MIDV [24:16]
+        * VPLL_CON: MIDV [24:16]
+        */
+       if (pllreg == APLL || pllreg == MPLL)
+               mask = 0x3ff;
+       else
+               mask = 0x1ff;
+
+       m = (r >> 16) & mask;
+
+       /* PDIV [13:8] */
+       p = (r >> 8) & 0x3f;
+       /* SDIV [2:0] */
+       s = r & 0x7;
+
+       freq = CONFIG_SYS_CLK_FREQ;
+
+       if (pllreg == EPLL) {
+               k = k & 0xffff;
+               /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
+               fout = (m + k / 65536) * (freq / (p * (1 << s)));
+       } else if (pllreg == VPLL) {
+               k = k & 0xfff;
+               /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
+               fout = (m + k / 1024) * (freq / (p * (1 << s)));
+       } else {
+               if (s < 1)
+                       s = 1;
+               /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
+               fout = m * (freq / (p * (1 << (s - 1))));
+       }
+
+       return fout;
+}
+
 /* exynos4: return ARM clock frequency */
 static unsigned long exynos4_get_arm_clk(void)
 {
@@ -114,6 +180,28 @@ static unsigned long exynos4_get_arm_clk(void)
        return armclk;
 }
 
+/* exynos5: return ARM clock frequency */
+static unsigned long exynos5_get_arm_clk(void)
+{
+       struct exynos5_clock *clk =
+               (struct exynos5_clock *)samsung_get_base_clock();
+       unsigned long div;
+       unsigned long armclk;
+       unsigned int arm_ratio;
+       unsigned int arm2_ratio;
+
+       div = readl(&clk->div_cpu0);
+
+       /* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */
+       arm_ratio = (div >> 0) & 0x7;
+       arm2_ratio = (div >> 28) & 0x7;
+
+       armclk = get_pll_clk(APLL) / (arm_ratio + 1);
+       armclk /= (arm2_ratio + 1);
+
+       return armclk;
+}
+
 /* exynos4: return pwm clock frequency */
 static unsigned long exynos4_get_pwm_clk(void)
 {
@@ -157,6 +245,27 @@ static unsigned long exynos4_get_pwm_clk(void)
        return pclk;
 }
 
+/* exynos5: return pwm clock frequency */
+static unsigned long exynos5_get_pwm_clk(void)
+{
+       struct exynos5_clock *clk =
+               (struct exynos5_clock *)samsung_get_base_clock();
+       unsigned long pclk, sclk;
+       unsigned int ratio;
+
+       /*
+        * CLK_DIV_PERIC3
+        * PWM_RATIO [3:0]
+        */
+       ratio = readl(&clk->div_peric3);
+       ratio = ratio & 0xf;
+       sclk = get_pll_clk(MPLL);
+
+       pclk = sclk / (ratio + 1);
+
+       return pclk;
+}
+
 /* exynos4: return uart clock frequency */
 static unsigned long exynos4_get_uart_clk(int dev_index)
 {
@@ -204,6 +313,53 @@ static unsigned long exynos4_get_uart_clk(int dev_index)
        return uclk;
 }
 
+/* exynos5: return uart clock frequency */
+static unsigned long exynos5_get_uart_clk(int dev_index)
+{
+       struct exynos5_clock *clk =
+               (struct exynos5_clock *)samsung_get_base_clock();
+       unsigned long uclk, sclk;
+       unsigned int sel;
+       unsigned int ratio;
+
+       /*
+        * CLK_SRC_PERIC0
+        * UART0_SEL [3:0]
+        * UART1_SEL [7:4]
+        * UART2_SEL [8:11]
+        * UART3_SEL [12:15]
+        * UART4_SEL [16:19]
+        * UART5_SEL [23:20]
+        */
+       sel = readl(&clk->src_peric0);
+       sel = (sel >> (dev_index << 2)) & 0xf;
+
+       if (sel == 0x6)
+               sclk = get_pll_clk(MPLL);
+       else if (sel == 0x7)
+               sclk = get_pll_clk(EPLL);
+       else if (sel == 0x8)
+               sclk = get_pll_clk(VPLL);
+       else
+               return 0;
+
+       /*
+        * CLK_DIV_PERIC0
+        * UART0_RATIO [3:0]
+        * UART1_RATIO [7:4]
+        * UART2_RATIO [8:11]
+        * UART3_RATIO [12:15]
+        * UART4_RATIO [16:19]
+        * UART5_RATIO [23:20]
+        */
+       ratio = readl(&clk->div_peric0);
+       ratio = (ratio >> (dev_index << 2)) & 0xf;
+
+       uclk = sclk / (ratio + 1);
+
+       return uclk;
+}
+
 /* exynos4: set the mmc clock */
 static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
 {
@@ -231,27 +387,69 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned 
int div)
        writel(val, addr);
 }
 
+/* exynos5: set the mmc clock */
+static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
+{
+       struct exynos5_clock *clk =
+               (struct exynos5_clock *)samsung_get_base_clock();
+       unsigned int addr;
+       unsigned int val;
+
+       /*
+        * CLK_DIV_FSYS1
+        * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
+        * CLK_DIV_FSYS2
+        * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
+        */
+       if (dev_index < 2) {
+               addr = (unsigned int)&clk->div_fsys1;
+       } else {
+               addr = (unsigned int)&clk->div_fsys2;
+               dev_index -= 2;
+       }
+
+       val = readl(addr);
+       val &= ~(0xff << ((dev_index << 4) + 8));
+       val |= (div & 0xff) << ((dev_index << 4) + 8);
+       writel(val, addr);
+}
+
 unsigned long get_pll_clk(int pllreg)
 {
-       return exynos4_get_pll_clk(pllreg);
+       if (cpu_is_exynos5())
+               return exynos5_get_pll_clk(pllreg);
+       else
+               return exynos4_get_pll_clk(pllreg);
 }
 
 unsigned long get_arm_clk(void)
 {
-       return exynos4_get_arm_clk();
+       if (cpu_is_exynos5())
+               return exynos5_get_arm_clk();
+       else
+               return exynos4_get_arm_clk();
 }
 
 unsigned long get_pwm_clk(void)
 {
-       return exynos4_get_pwm_clk();
+       if (cpu_is_exynos5())
+               return exynos5_get_pwm_clk();
+       else
+               return exynos4_get_pwm_clk();
 }
 
 unsigned long get_uart_clk(int dev_index)
 {
-       return exynos4_get_uart_clk(dev_index);
+       if (cpu_is_exynos5())
+               return exynos5_get_uart_clk(dev_index);
+       else
+               return exynos4_get_uart_clk(dev_index);
 }
 
 void set_mmc_clk(int dev_index, unsigned int div)
 {
-       exynos4_set_mmc_clk(dev_index, div);
+       if (cpu_is_exynos5())
+               exynos5_set_mmc_clk(dev_index, div);
+       else
+               exynos4_set_mmc_clk(dev_index, div);
 }
diff --git a/arch/arm/include/asm/arch-exynos/clock.h 
b/arch/arm/include/asm/arch-exynos/clock.h
index 483c911..50da958 100644
--- a/arch/arm/include/asm/arch-exynos/clock.h
+++ b/arch/arm/include/asm/arch-exynos/clock.h
@@ -250,6 +250,332 @@ struct exynos4_clock {
        unsigned int    div_iem_l2;
        unsigned int    div_iem_l1;
 };
+
+struct exynos5_clock {
+       unsigned int    apll_lock;
+       unsigned char   res1[0xfc];
+       unsigned int    apll_con0;
+       unsigned int    apll_con1;
+       unsigned char   res2[0xf8];
+       unsigned int    src_cpu;
+       unsigned char   res3[0x1fc];
+       unsigned int    mux_stat_cpu;
+       unsigned char   res4[0xfc];
+       unsigned int    div_cpu0;
+       unsigned int    div_cpu1;
+       unsigned char   res5[0xf8];
+       unsigned int    div_stat_cpu0;
+       unsigned int    div_stat_cpu1;
+       unsigned char   res6[0x1f8];
+       unsigned int    gate_sclk_cpu;
+       unsigned char   res7[0x1fc];
+       unsigned int    clkout_cmu_cpu;
+       unsigned int    clkout_cmu_cpu_div_stat;
+       unsigned char   res8[0x5f8];
+       unsigned int    armclk_stopctrl;
+       unsigned int    atclk_stopctrl;
+       unsigned char   res9[0x8];
+       unsigned int    parityfail_status;
+       unsigned int    parityfail_clear;
+       unsigned char   res10[0x8];
+       unsigned int    pwr_ctrl;
+       unsigned int    pwr_ctr2;
+       unsigned char   res11[0xd8];
+       unsigned int    apll_con0_l8;
+       unsigned int    apll_con0_l7;
+       unsigned int    apll_con0_l6;
+       unsigned int    apll_con0_l5;
+       unsigned int    apll_con0_l4;
+       unsigned int    apll_con0_l3;
+       unsigned int    apll_con0_l2;
+       unsigned int    apll_con0_l1;
+       unsigned int    iem_control;
+       unsigned char   res12[0xdc];
+       unsigned int    apll_con1_l8;
+       unsigned int    apll_con1_l7;
+       unsigned int    apll_con1_l6;
+       unsigned int    apll_con1_l5;
+       unsigned int    apll_con1_l4;
+       unsigned int    apll_con1_l3;
+       unsigned int    apll_con1_l2;
+       unsigned int    apll_con1_l1;
+       unsigned char   res13[0xe0];
+       unsigned int    div_iem_l8;
+       unsigned int    div_iem_l7;
+       unsigned int    div_iem_l6;
+       unsigned int    div_iem_l5;
+       unsigned int    div_iem_l4;
+       unsigned int    div_iem_l3;
+       unsigned int    div_iem_l2;
+       unsigned int    div_iem_l1;
+       unsigned char   res14[0x2ce0];
+       unsigned int    mpll_lock;
+       unsigned char   res15[0xfc];
+       unsigned int    mpll_con0;
+       unsigned int    mpll_con1;
+       unsigned char   res16[0xf8];
+       unsigned int    src_core0;
+       unsigned int    src_core1;
+       unsigned char   res17[0xf8];
+       unsigned int    src_mask_core;
+       unsigned char   res18[0x100];
+       unsigned int    mux_stat_core1;
+       unsigned char   res19[0xf8];
+       unsigned int    div_core0;
+       unsigned int    div_core1;
+       unsigned char   res20[0xf8];
+       unsigned int    div_stat_core0;
+       unsigned int    div_stat_core1;
+       unsigned char   res21[0x2f8];
+       unsigned int    gate_ip_core;
+       unsigned char   res22[0xfc];
+       unsigned int    clkout_cmu_core;
+       unsigned int    clkout_cmu_core_div_stat;
+       unsigned char   res23[0x5f8];
+       unsigned int    dcgidx_map0;
+       unsigned int    dcgidx_map1;
+       unsigned int    dcgidx_map2;
+       unsigned char   res24[0x14];
+       unsigned int    dcgperf_map0;
+       unsigned int    dcgperf_map1;
+       unsigned char   res25[0x18];
+       unsigned int    dvcidx_map;
+       unsigned char   res26[0x1c];
+       unsigned int    freq_cpu;
+       unsigned int    freq_dpm;
+       unsigned char   res27[0x18];
+       unsigned int    dvsemclk_en;
+       unsigned int    maxperf;
+       unsigned char   res28[0x3478];
+       unsigned int    div_acp;
+       unsigned char   res29[0xfc];
+       unsigned int    div_stat_acp;
+       unsigned char   res30[0x1fc];
+       unsigned int    gate_ip_acp;
+       unsigned char   res31[0x1fc];
+       unsigned int    clkout_cmu_acp;
+       unsigned int    clkout_cmu_acp_div_stat;
+       unsigned char   res32[0x38f8];
+       unsigned int    div_isp0;
+       unsigned int    div_isp1;
+       unsigned int    div_isp2;
+       unsigned char   res33[0xf4];
+       unsigned int    div_stat_isp0;
+       unsigned int    div_stat_isp1;
+       unsigned int    div_stat_isp2;
+       unsigned char   res34[0x3f4];
+       unsigned int    gate_ip_isp0;
+       unsigned int    gate_ip_isp1;
+       unsigned char   res35[0xf8];
+       unsigned int    gate_sclk_isp;
+       unsigned char   res36[0xc];
+       unsigned int    mcuisp_pwr_ctrl;
+       unsigned char   res37[0xec];
+       unsigned int    clkout_cmu_isp;
+       unsigned int    clkout_cmu_isp_div_stat;
+       unsigned char   res38[0x3618];
+       unsigned int    cpll_lock;
+       unsigned char   res39[0xc];
+       unsigned int    epll_lock;
+       unsigned char   res40[0xc];
+       unsigned int    vpll_lock;
+       unsigned char   res41[0xdc];
+       unsigned int    cpll_con0;
+       unsigned int    cpll_con1;
+       unsigned char   res42[0x8];
+       unsigned int    epll_con0;
+       unsigned int    epll_con1;
+       unsigned int    epll_con2;
+       unsigned char   res43[0x4];
+       unsigned int    vpll_con0;
+       unsigned int    vpll_con1;
+       unsigned int    vpll_con2;
+       unsigned char   res44[0xc4];
+       unsigned int    src_top0;
+       unsigned int    src_top1;
+       unsigned int    src_top2;
+       unsigned int    src_top3;
+       unsigned int    src_gscl;
+       unsigned int    src_disp0_0;
+       unsigned int    src_disp0_1;
+       unsigned int    src_disp1_0;
+       unsigned int    src_disp1_1;
+       unsigned char   res46[0xc];
+       unsigned int    src_mau;
+       unsigned int    src_fsys;
+       unsigned char   res47[0x8];
+       unsigned int    src_peric0;
+       unsigned int    src_peric1;
+       unsigned char   res48[0x18];
+       unsigned int    sclk_src_isp;
+       unsigned char   res49[0x9c];
+       unsigned int    src_mask_top;
+       unsigned char   res50[0xc];
+       unsigned int    src_mask_gscl;
+       unsigned int    src_mask_disp0_0;
+       unsigned int    src_mask_disp0_1;
+       unsigned int    src_mask_disp1_0;
+       unsigned int    src_mask_disp1_1;
+       unsigned int    src_mask_maudio;
+       unsigned char   res52[0x8];
+       unsigned int    src_mask_fsys;
+       unsigned char   res53[0xc];
+       unsigned int    src_mask_peric0;
+       unsigned int    src_mask_peric1;
+       unsigned char   res54[0x18];
+       unsigned int    src_mask_isp;
+       unsigned char   res55[0x9c];
+       unsigned int    mux_stat_top0;
+       unsigned int    mux_stat_top1;
+       unsigned int    mux_stat_top2;
+       unsigned int    mux_stat_top3;
+       unsigned char   res56[0xf0];
+       unsigned int    div_top0;
+       unsigned int    div_top1;
+       unsigned char   res57[0x8];
+       unsigned int    div_gscl;
+       unsigned int    div_disp0_0;
+       unsigned int    div_disp0_1;
+       unsigned int    div_disp1_0;
+       unsigned int    div_disp1_1;
+       unsigned char   res59[0x8];
+       unsigned int    div_gen;
+       unsigned char   res60[0x4];
+       unsigned int    div_mau;
+       unsigned int    div_fsys0;
+       unsigned int    div_fsys1;
+       unsigned int    div_fsys2;
+       unsigned int    div_fsys3;
+       unsigned int    div_peric0;
+       unsigned int    div_peric1;
+       unsigned int    div_peric2;
+       unsigned int    div_peric3;
+       unsigned int    div_peric4;
+       unsigned int    div_peric5;
+       unsigned char   res61[0x10];
+       unsigned int    sclk_div_isp;
+       unsigned char   res62[0xc];
+       unsigned int    div2_ratio0;
+       unsigned int    div2_ratio1;
+       unsigned char   res63[0x8];
+       unsigned int    div4_ratio;
+       unsigned char   res64[0x6c];
+       unsigned int    div_stat_top0;
+       unsigned int    div_stat_top1;
+       unsigned char   res65[0x8];
+       unsigned int    div_stat_gscl;
+       unsigned int    div_stat_disp0_0;
+       unsigned int    div_stat_disp0_1;
+       unsigned int    div_stat_disp1_0;
+       unsigned int    div_stat_disp1_1;
+       unsigned char   res67[0x8];
+       unsigned int    div_stat_gen;
+       unsigned char   res68[0x4];
+       unsigned int    div_stat_maudio;
+       unsigned int    div_stat_fsys0;
+       unsigned int    div_stat_fsys1;
+       unsigned int    div_stat_fsys2;
+       unsigned int    div_stat_fsys3;
+       unsigned int    div_stat_peric0;
+       unsigned int    div_stat_peric1;
+       unsigned int    div_stat_peric2;
+       unsigned int    div_stat_peric3;
+       unsigned int    div_stat_peric4;
+       unsigned int    div_stat_peric5;
+       unsigned char   res69[0x10];
+       unsigned int    sclk_div_stat_isp;
+       unsigned char   res70[0xc];
+       unsigned int    div2_stat0;
+       unsigned int    div2_stat1;
+       unsigned char   res71[0x8];
+       unsigned int    div4_stat;
+       unsigned char   res72[0x180];
+       unsigned int    gate_top_sclk_disp0;
+       unsigned int    gate_top_sclk_disp1;
+       unsigned int    gate_top_sclk_gen;
+       unsigned char   res74[0xc];
+       unsigned int    gate_top_sclk_mau;
+       unsigned int    gate_top_sclk_fsys;
+       unsigned char   res75[0xc];
+       unsigned int    gate_top_sclk_peric;
+       unsigned char   res76[0x1c];
+       unsigned int    gate_top_sclk_isp;
+       unsigned char   res77[0xac];
+       unsigned int    gate_ip_gscl;
+       unsigned int    gate_ip_disp0;
+       unsigned int    gate_ip_disp1;
+       unsigned int    gate_ip_mfc;
+       unsigned int    gate_ip_g3d;
+       unsigned int    gate_ip_gen;
+       unsigned char   res79[0xc];
+       unsigned int    gate_ip_fsys;
+       unsigned char   res80[0x4];
+       unsigned int    gate_ip_gps;
+       unsigned int    gate_ip_peric;
+       unsigned char   res81[0xc];
+       unsigned int    gate_ip_peris;
+       unsigned char   res82[0x1c];
+       unsigned int    gate_block;
+       unsigned char   res83[0x7c];
+       unsigned int    clkout_cmu_top;
+       unsigned int    clkout_cmu_top_div_stat;
+       unsigned char   res84[0x37f8];
+       unsigned int    src_lex;
+       unsigned char   res85[0x2fc];
+       unsigned int    div_lex;
+       unsigned char   res86[0xfc];
+       unsigned int    div_stat_lex;
+       unsigned char   res87[0x1fc];
+       unsigned int    gate_ip_lex;
+       unsigned char   res88[0x1fc];
+       unsigned int    clkout_cmu_lex;
+       unsigned int    clkout_cmu_lex_div_stat;
+       unsigned char   res89[0x3af8];
+       unsigned int    div_r0x;
+       unsigned char   res90[0xfc];
+       unsigned int    div_stat_r0x;
+       unsigned char   res91[0x1fc];
+       unsigned int    gate_ip_r0x;
+       unsigned char   res92[0x1fc];
+       unsigned int    clkout_cmu_r0x;
+       unsigned int    clkout_cmu_r0x_div_stat;
+       unsigned char   res94[0x3af8];
+       unsigned int    div_r1x;
+       unsigned char   res95[0xfc];
+       unsigned int    div_stat_r1x;
+       unsigned char   res96[0x1fc];
+       unsigned int    gate_ip_r1x;
+       unsigned char   res97[0x1fc];
+       unsigned int    clkout_cmu_r1x;
+       unsigned int    clkout_cmu_r1x_div_stat;
+       unsigned char   res98[0x3608];
+       unsigned int    bpll_lock;
+       unsigned char   res99[0xfc];
+       unsigned int    bpll_con0;
+       unsigned int    bpll_con1;
+       unsigned char   res100[0xe8];
+       unsigned int    src_cdrex;
+       unsigned char   res101[0x1fc];
+       unsigned int    mux_stat_cdrex;
+       unsigned char   res102[0xfc];
+       unsigned int    div_cdrex;
+       unsigned int    div_cdrex2;
+       unsigned char   res103[0xf8];
+       unsigned int    div_stat_cdrex;
+       unsigned char   res104[0x2fc];
+       unsigned int    gate_ip_cdrex;
+       unsigned char   res105[0xc];
+       unsigned int    c2c_monitor;
+       unsigned int    dmc_pwr_ctrl;
+       unsigned char   res106[0x4];
+       unsigned int    drex2_pause;
+       unsigned char   res107[0xe0];
+       unsigned int    clkout_cmu_cdrex;
+       unsigned int    clkout_cmu_cdrex_div_stat;
+       unsigned char   res108[0x8];
+       unsigned int    lpddr3phy_ctrl;
+       unsigned char   res109[0xf5f8];
+};
 #endif
 
 #endif
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h 
b/arch/arm/include/asm/arch-exynos/cpu.h
index 3496616..89f2c2e 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -22,6 +22,8 @@
 #ifndef _EXYNOS4_CPU_H
 #define _EXYNOS4_CPU_H
 
+#define DEVICE_NOT_AVAILABLE           0
+
 #define EXYNOS4_ADDR_BASE              0x10000000
 
 /* EXYNOS4 */
@@ -46,7 +48,34 @@
 #define EXYNOS4_ADC_BASE               0x13910000
 #define EXYNOS4_PWMTIMER_BASE          0x139D0000
 #define EXYNOS4_MODEM_BASE             0x13A00000
-#define EXYNOS4_USBPHY_CONTROL          0x10020704
+#define EXYNOS4_USBPHY_CONTROL         0x10020704
+
+#define EXYNOS4_GPIO_PART4_BASE                DEVICE_NOT_AVAILABLE
+
+/* EXYNOS5 */
+#define EXYNOS5_GPIO_PART4_BASE                0x03860000
+#define EXYNOS5_PRO_ID                 0x10000000
+#define EXYNOS5_CLOCK_BASE             0x10010000
+#define EXYNOS5_POWER_BASE             0x10040000
+#define EXYNOS5_SWRESET                        0x10040400
+#define EXYNOS5_SYSREG_BASE            0x10050000
+#define EXYNOS5_WATCHDOG_BASE          0x101D0000
+#define EXYNOS5_DMC_PHY0_BASE          0x10C00000
+#define EXYNOS5_DMC_PHY1_BASE          0x10C10000
+#define EXYNOS5_GPIO_PART3_BASE                0x10D10000
+#define EXYNOS5_DMC_CTRL_BASE          0x10DD0000
+#define EXYNOS5_GPIO_PART1_BASE                0x11400000
+#define EXYNOS5_MMC_BASE               0x12200000
+#define EXYNOS5_SROMC_BASE             0x12250000
+#define EXYNOS5_USBOTG_BASE            0x12480000
+#define EXYNOS5_USBPHY_BASE            0x12480000
+#define EXYNOS5_UART_BASE              0x12C00000
+#define EXYNOS5_PWMTIMER_BASE          0x12DD0000
+#define EXYNOS5_GPIO_PART2_BASE                0x13400000
+#define EXYNOS5_FIMD_BASE              0x14400000
+
+#define EXYNOS5_ADC_BASE               DEVICE_NOT_AVAILABLE
+#define EXYNOS5_MODEM_BASE             DEVICE_NOT_AVAILABLE
 
 #ifndef __ASSEMBLY__
 #include <asm/io.h>
@@ -83,12 +112,15 @@ static inline int cpu_is_##type(void)                      
\
 }
 
 IS_SAMSUNG_TYPE(exynos4, 0xc210)
+IS_SAMSUNG_TYPE(exynos5, 0xc520)
 
 #define SAMSUNG_BASE(device, base)                             \
 static inline unsigned int samsung_get_base_##device(void)     \
 {                                                              \
        if (cpu_is_exynos4())                                   \
                return EXYNOS4_##base;                          \
+       else if (cpu_is_exynos5())                              \
+               return EXYNOS5_##base;                          \
        else                                                    \
                return 0;                                       \
 }
@@ -99,6 +131,7 @@ SAMSUNG_BASE(fimd, FIMD_BASE)
 SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE)
 SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE)
 SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE)
+SAMSUNG_BASE(gpio_part4, GPIO_PART4_BASE)
 SAMSUNG_BASE(pro_id, PRO_ID)
 SAMSUNG_BASE(mmc, MMC_BASE)
 SAMSUNG_BASE(modem, MODEM_BASE)
diff --git a/arch/arm/include/asm/arch-exynos/dmc.h 
b/arch/arm/include/asm/arch-exynos/dmc.h
new file mode 100644
index 0000000..debbe50
--- /dev/null
+++ b/arch/arm/include/asm/arch-exynos/dmc.h
@@ -0,0 +1,146 @@
+#ifndef __DMC_H__
+#define __DMC_H__
+
+#ifndef __ASSEMBLY__
+struct exynos5_dmc {
+       unsigned int concontrol;
+       unsigned int memcontrol;
+       unsigned int memconfig0;
+       unsigned int memconfig1;
+       unsigned int directcmd;
+       unsigned int prechconfig;
+       unsigned int phycontrol0;
+       unsigned char res1[0xc];
+       unsigned int pwrdnconfig;
+       unsigned int timingpzq;
+       unsigned int timingref;
+       unsigned int timingrow;
+       unsigned int timingdata;
+       unsigned int timingpower;
+       unsigned int phystatus;
+       unsigned char res2[0x4];
+       unsigned int chipstatus_ch0;
+       unsigned int chipstatus_ch1;
+       unsigned char res3[0x4];
+       unsigned int mrstatus;
+       unsigned char res4[0x8];
+       unsigned int qoscontrol0;
+       unsigned char resr5[0x4];
+       unsigned int qoscontrol1;
+       unsigned char res6[0x4];
+       unsigned int qoscontrol2;
+       unsigned char res7[0x4];
+       unsigned int qoscontrol3;
+       unsigned char res8[0x4];
+       unsigned int qoscontrol4;
+       unsigned char res9[0x4];
+       unsigned int qoscontrol5;
+       unsigned char res10[0x4];
+       unsigned int qoscontrol6;
+       unsigned char res11[0x4];
+       unsigned int qoscontrol7;
+       unsigned char res12[0x4];
+       unsigned int qoscontrol8;
+       unsigned char res13[0x4];
+       unsigned int qoscontrol9;
+       unsigned char res14[0x4];
+       unsigned int qoscontrol10;
+       unsigned char res15[0x4];
+       unsigned int qoscontrol11;
+       unsigned char res16[0x4];
+       unsigned int qoscontrol12;
+       unsigned char res17[0x4];
+       unsigned int qoscontrol13;
+       unsigned char res18[0x4];
+       unsigned int qoscontrol14;
+       unsigned char res19[0x4];
+       unsigned int qoscontrol15;
+       unsigned char res20[0x14];
+       unsigned int ivcontrol;
+       unsigned int wrtra_config;
+       unsigned int rdlvl_config;
+       unsigned char res21[0x8];
+       unsigned int brbrsvconfig;
+       unsigned int brbqosconfig;
+       unsigned int membaseconfig0;
+       unsigned int membaseconfig1;
+       unsigned char res22[0xc];
+       unsigned int wrlvl_config;
+       unsigned char res23[0xc];
+       unsigned int perevcontrol;
+       unsigned int perev0config;
+       unsigned int perev1config;
+       unsigned int perev2config;
+       unsigned int perev3config;
+       unsigned char res24[0xdebc];
+       unsigned int pmnc_ppc_a;
+       unsigned char res25[0xc];
+       unsigned int cntens_ppc_a;
+       unsigned char res26[0xc];
+       unsigned int cntenc_ppc_a;
+       unsigned char res27[0xc];
+       unsigned int intens_ppc_a;
+       unsigned char res28[0xc];
+       unsigned int intenc_ppc_a;
+       unsigned char res29[0xc];
+       unsigned int flag_ppc_a;
+       unsigned char res30[0xac];
+       unsigned int ccnt_ppc_a;
+       unsigned char res31[0xc];
+       unsigned int pmcnt0_ppc_a;
+       unsigned char res32[0xc];
+       unsigned int pmcnt1_ppc_a;
+       unsigned char res33[0xc];
+       unsigned int pmcnt2_ppc_a;
+       unsigned char res34[0xc];
+       unsigned int pmcnt3_ppc_a;
+};
+
+struct exynos5_phy_control {
+       unsigned int phy_con0;
+       unsigned int phy_con1;
+       unsigned int phy_con2;
+       unsigned int phy_con3;
+       unsigned int phy_con4;
+       unsigned char res1[4];
+       unsigned int phy_con6;
+       unsigned char res2[4];
+       unsigned int phy_con8;
+       unsigned int phy_con9;
+       unsigned int phy_con10;
+       unsigned char res3[4];
+       unsigned int phy_con12;
+       unsigned int phy_con13;
+       unsigned int phy_con14;
+       unsigned int phy_con15;
+       unsigned int phy_con16;
+       unsigned char res4[4];
+       unsigned int phy_con17;
+       unsigned int phy_con18;
+       unsigned int phy_con19;
+       unsigned int phy_con20;
+       unsigned int phy_con21;
+       unsigned int phy_con22;
+       unsigned int phy_con23;
+       unsigned int phy_con24;
+       unsigned int phy_con25;
+       unsigned int phy_con26;
+       unsigned int phy_con27;
+       unsigned int phy_con28;
+       unsigned int phy_con29;
+       unsigned int phy_con30;
+       unsigned int phy_con31;
+       unsigned int phy_con32;
+       unsigned int phy_con33;
+       unsigned int phy_con34;
+       unsigned int phy_con35;
+       unsigned int phy_con36;
+       unsigned int phy_con37;
+       unsigned int phy_con38;
+       unsigned int phy_con39;
+       unsigned int phy_con40;
+       unsigned int phy_con41;
+       unsigned int phy_con42;
+};
+#endif
+#endif
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h 
b/arch/arm/include/asm/arch-exynos/gpio.h
index 9863a12..7a9bb90 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -79,6 +79,59 @@ struct exynos4_gpio_part3 {
        struct s5p_gpio_bank z;
 };
 
+struct exynos5_gpio_part1 {
+       struct s5p_gpio_bank a0;
+       struct s5p_gpio_bank a1;
+       struct s5p_gpio_bank a2;
+       struct s5p_gpio_bank b0;
+       struct s5p_gpio_bank b1;
+       struct s5p_gpio_bank b2;
+       struct s5p_gpio_bank b3;
+       struct s5p_gpio_bank c0;
+       struct s5p_gpio_bank c1;
+       struct s5p_gpio_bank c2;
+       struct s5p_gpio_bank c3;
+       struct s5p_gpio_bank d0;
+       struct s5p_gpio_bank d1;
+       struct s5p_gpio_bank y0;
+       struct s5p_gpio_bank y1;
+       struct s5p_gpio_bank y2;
+       struct s5p_gpio_bank y3;
+       struct s5p_gpio_bank y4;
+       struct s5p_gpio_bank y5;
+       struct s5p_gpio_bank y6;
+       struct s5p_gpio_bank res1[0x980];
+       struct s5p_gpio_bank x0;
+       struct s5p_gpio_bank x1;
+       struct s5p_gpio_bank x2;
+       struct s5p_gpio_bank x3;
+};
+
+struct exynos5_gpio_part2 {
+       struct s5p_gpio_bank e0;
+       struct s5p_gpio_bank e1;
+       struct s5p_gpio_bank f0;
+       struct s5p_gpio_bank f1;
+       struct s5p_gpio_bank g0;
+       struct s5p_gpio_bank g1;
+       struct s5p_gpio_bank g2;
+       struct s5p_gpio_bank h0;
+       struct s5p_gpio_bank h1;
+};
+
+struct exynos5_gpio_part3 {
+       struct s5p_gpio_bank v0;
+       struct s5p_gpio_bank v1;
+       struct s5p_gpio_bank v2;
+       struct s5p_gpio_bank v3;
+       struct s5p_gpio_bank res1[0x20];
+       struct s5p_gpio_bank v4;
+};
+
+struct exynos5_gpio_part4 {
+       struct s5p_gpio_bank z;
+};
+
 /* functions */
 void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
 void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
@@ -98,21 +151,55 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int 
gpio, int mode);
            - EXYNOS4_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
          * GPIO_PER_BANK) + pin)
 
-#define GPIO_PART1_MAX ((sizeof(struct exynos4_gpio_part1) \
+#define EXYNOS4_GPIO_PART1_MAX ((sizeof(struct exynos4_gpio_part1) \
                            / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
 
 #define exynos4_gpio_part2_get_nr(bank, pin) \
        (((((((unsigned int) &(((struct exynos4_gpio_part2 *) \
                                EXYNOS4_GPIO_PART2_BASE)->bank)) \
            - EXYNOS4_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
-         * GPIO_PER_BANK) + pin) + GPIO_PART1_MAX)
+         * GPIO_PER_BANK) + pin) + EXYNOS4_GPIO_PART1_MAX)
+
+#define exynos5_gpio_part1_get_nr(bank, pin) \
+       ((((((unsigned int) &(((struct exynos5_gpio_part1 *) \
+                              EXYNOS5_GPIO_PART1_BASE)->bank)) \
+           - EXYNOS5_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
+         * GPIO_PER_BANK) + pin)
+
+#define EXYNOS5_GPIO_PART1_MAX ((sizeof(struct exynos5_gpio_part1) \
+                           / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
+
+#define exynos5_gpio_part2_get_nr(bank, pin) \
+       (((((((unsigned int) &(((struct exynos5_gpio_part2 *) \
+                               EXYNOS5_GPIO_PART2_BASE)->bank)) \
+           - EXYNOS5_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
+         * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART1_MAX)
+
+#define EXYNOS5_GPIO_PART2_MAX ((sizeof(struct exynos5_gpio_part2) \
+                           / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
+
+#define exynos5_gpio_part3_get_nr(bank, pin) \
+       (((((((unsigned int) &(((struct exynos5_gpio_part3 *) \
+                               EXYNOS5_GPIO_PART3_BASE)->bank)) \
+           - EXYNOS5_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
+         * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART2_MAX)
 
 static inline unsigned int s5p_gpio_base(int nr)
 {
-       if (nr < GPIO_PART1_MAX)
-               return EXYNOS4_GPIO_PART1_BASE;
-       else
-               return EXYNOS4_GPIO_PART2_BASE;
+       if (cpu_is_exynos5()) {
+               if (nr < EXYNOS5_GPIO_PART1_MAX)
+                       return EXYNOS5_GPIO_PART1_BASE;
+               else if (nr < EXYNOS5_GPIO_PART2_MAX)
+                       return EXYNOS5_GPIO_PART2_BASE;
+               else
+                       return EXYNOS5_GPIO_PART3_BASE;
+
+       } else if (cpu_is_exynos4()) {
+               if (nr < EXYNOS4_GPIO_PART1_MAX)
+                       return EXYNOS4_GPIO_PART1_BASE;
+               else
+                       return EXYNOS4_GPIO_PART2_BASE;
+       }
 
        return 0;
 }
diff --git a/arch/arm/include/asm/arch-exynos/tzpc.h 
b/arch/arm/include/asm/arch-exynos/tzpc.h
new file mode 100644
index 0000000..2c9a07b
--- /dev/null
+++ b/arch/arm/include/asm/arch-exynos/tzpc.h
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2012 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __TZPC_H_
+#define __TZPC_H_
+
+#ifndef __ASSEMBLY__
+struct exynos5_tzpc {
+       unsigned int r0size;
+       char res1[0x7FC];
+       unsigned int decprot0stat;
+       unsigned int decprot0set;
+       unsigned int decprot0clr;
+       unsigned int decprot1stat;
+       unsigned int decprot1set;
+       unsigned int decprot1clr;
+       unsigned int decprot2stat;
+       unsigned int decprot2set;
+       unsigned int decprot2clr;
+       unsigned int decprot3stat;
+       unsigned int decprot3set;
+       unsigned int decprot3clr;
+       char res2[0x7B0];
+       unsigned int periphid0;
+       unsigned int periphid1;
+       unsigned int periphid2;
+       unsigned int periphid3;
+       unsigned int pcellid0;
+       unsigned int pcellid1;
+       unsigned int pcellid2;
+       unsigned int pcellid3;
+};
+#endif
+
+#endif
-- 
1.7.5.4


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