== Progress == * [ARM GlobalISel] Use CC support for lowering args/return [TCWG-946] [2/10] - Committed patch extracting target-independent functionality from AArch64 GlobalISel - Submitted patch using that functionality to lower any number of i32 arguments - Refactored [ARM GlobalISel] Select add instructions [TCWG-925] to also use the extracted functionality
* [ARM GlobalISel] Add support for integers < 32 bits wide [TCWG-980] [4/10] - Support for lowering i8 and i16 arguments / returns through registers is ready, including the ABI signext / zeroext - Currently brushing up i1 * Rewrite llvm-projs in Python [TCWG-833] [2/10] - Refactored patch a bit based on feedback from reviews, still have some refactoring left to do - Fixed a bug related to worktree detection * Misc [2/10] - Meetings, mailing lists, code reviews == Plan == * Ping / rebase upstream patches * [ARM GlobalISel] Add support for integers < 32 bits wide [TCWG-980] - Finish i1 through registers - Implement i1, i8, i16 through the stack * Rewrite llvm-projs in Python [TCWG-833] - Finish refactoring _______________________________________________ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
