> Not if the two CPUs are different architectures. For different > processors of the same architecture, yes, more or less.
Even then it doesn't work. During my PCM career (1978-1992) I lost count of the number of times silly amateurs wrote little kernel loops, didn't see what they simplisticly expected, and created no end of pointless work for me to explain their results. Example - the 3033S was degraded from the 3033U simply by reducing the HSB to 512 bytes. If you wrote a kernel that was small enough to fit in 512 bytes - not hard - you would see EXACTLY the same performance on a 3033S as on a 3033U. We all learned from that, so degrading (known in some circles as "golden screwdrivering") became more complex - idle cycles were inserted in microcode, etc. Even this wasn't enough. Hitachi degraded the S8 processor (marketed in the USA as the NAS AS/9000 series) in part by inserting idle cycles in the I-stage of the pipeline for certain instructions. But if the degraded instruction followed an instruction that took several E-stage cycles, the degradation was masked. I had a customer who upgraded a system and saw no improvement in his silly little kernel - he wouldn't have, because the idle cycles were deleted from an instruction that was waiting for the E-unit anyway. General rule of benchmarking - silly little kernels ALWAYS give erroneous results. -- Phil Payne http://www.isham-research.com +44 7785 302 803 +49 173 6242039
