Currently L1_CACHE_BYTES is defined as 32 for ev6. Increasing this
to 64 (as it should be) broke networking.
Most probably the reason is in the entry.S:
ret_from_sys_call:
cmovne $26,0,$19 /* $19 = 0 => non-restartable */
ldl $3,TASK_PROCESSOR($8)
lda $4,softirq_state
sll $3,5,$3
^^^^^^^^^^^^^^^
addq $3,$4,$4
ldq $4,0($4)
...
sizeof(struct softirq_state) hardcoded to 32 here, although
it depends on SMP_CACHE_BYTES (see include/linux/interrupt.h).
Could someone try this patch on ev6 SMP boxes?
Ivan.
diff -ur 2.4.0t5/arch/alpha/kernel/entry.S linux/arch/alpha/kernel/entry.S
--- 2.4.0t5/arch/alpha/kernel/entry.S Tue Jul 25 09:46:40 2000
+++ linux/arch/alpha/kernel/entry.S Mon Jul 31 17:40:30 2000
@@ -6,6 +6,7 @@
#include <linux/config.h>
#include <asm/system.h>
+#include <asm/cache.h>
#define SIGCHLD 20
@@ -577,7 +578,7 @@
cmovne $26,0,$19 /* $19 = 0 => non-restartable */
ldl $3,TASK_PROCESSOR($8)
lda $4,softirq_state
- sll $3,5,$3
+ sll $3,L1_CACHE_SHIFT,$3
addq $3,$4,$4
ldq $4,0($4)
sll $4,32,$3
diff -ur 2.4.0t5/include/asm-alpha/cache.h linux/include/asm-alpha/cache.h
--- 2.4.0t5/include/asm-alpha/cache.h Thu Jun 22 09:30:59 2000
+++ linux/include/asm-alpha/cache.h Mon Jul 31 17:51:11 2000
@@ -8,12 +8,14 @@
/* Bytes per L1 (data) cache line. */
#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EV6)
-# define L1_CACHE_BYTES 32 /* should be 64, but networking dies */
+# define L1_CACHE_BYTES 64
+# define L1_CACHE_SHIFT 6
#else
/* Both EV4 and EV5 are write-through, read-allocate,
direct-mapped, physical.
*/
# define L1_CACHE_BYTES 32
+# define L1_CACHE_SHIFT 5
#endif
#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
