Hi Stephen,

On 25/07/13 01:43, Stephen Boyd wrote:
> Some of Qualcomm's clocks can change their parent and rate at the
> same time with a single register write. Add support for this
> hardware to the common clock framework by adding a new
> set_rate_and_parent() op. When the clock framework determines
> that both the parent and the rate are going to change during
> clk_set_rate() it will call the .set_rate_and_parent() op if
> available and fall back to calling .set_parent() followed by
> .set_rate() otherwise.
> 
> Cc: James Hogan <james.ho...@imgtec.com>
> Signed-off-by: Stephen Boyd <sb...@codeaurora.org>

Aside from the nit below, I can't see anything wrong with this patch.
Reviewed-by: James Hogan <james.ho...@imgtec.com>

> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> index 484f8ad..1f7eabb 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -108,6 +108,18 @@ struct clk_hw;
>   *           which is likely helpful for most .set_rate implementation.
>   *           Returns 0 on success, -EERROR otherwise.
>   *
> + * @set_rate_and_parent: Change the rate and the parent of this clock. The
> + *           requested rate is specified by the second argument, which
> + *           should typically be the return of .round_rate call.  The
> + *           third argument gives the parent rate which is likely helpful
> + *           for most .set_rate_and_parent implementation. The fourth
> + *           argument gives the parent index. It is optional (and

nit: s/It/This callback/ or add newline or something - I completely
misread it the first time, thinking you were referring to the parent
index argument :)

> + *           unnecessary) for clocks with 0 or 1 parents as well as
> + *           for clocks that can tolerate switching the rate and the parent
> + *           separately via calls to .set_parent and .set_rate.
> + *           Returns 0 on success, -EERROR otherwise.
> + *
> + *
>   * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
>   * implementations to split any work between atomic (enable) and sleepable
>   * (prepare) contexts.  If enabling a clock requires code that might sleep,

Thanks
James

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