Some upcoming targets have more bits to set in CTL_FLUSH registers. Example: msm8x16 needs to set TIMING1 bit so that some of the INTF1's interface registers get flushed.
Signed-off-by: Stephane Viau <sv...@codeaurora.org> --- rnndb/mdp/mdp5.xml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/rnndb/mdp/mdp5.xml b/rnndb/mdp/mdp5.xml index 423249a..03dcc3a 100644 --- a/rnndb/mdp/mdp5.xml +++ b/rnndb/mdp/mdp5.xml @@ -250,11 +250,19 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <bitfield name="DSPP0" pos="13" type="boolean"/> <bitfield name="DSPP1" pos="14" type="boolean"/> <bitfield name="DSPP2" pos="15" type="boolean"/> + <bitfield name="WB" pos="16" type="boolean"/> <bitfield name="CTL" pos="17" type="boolean"/> <bitfield name="VIG3" pos="18" type="boolean"/> <bitfield name="RGB3" pos="19" type="boolean"/> <bitfield name="LM5" pos="20" type="boolean"/> <bitfield name="DSPP3" pos="21" type="boolean"/> + <bitfield name="CURSOR_0" pos="22" type="boolean"/> + <bitfield name="CURSOR_1" pos="23" type="boolean"/> + <bitfield name="CHROMADOWN_0" pos="26" type="boolean"/> + <bitfield name="TIMING_3" pos="28" type="boolean"/> + <bitfield name="TIMING_2" pos="29" type="boolean"/> + <bitfield name="TIMING_1" pos="30" type="boolean"/> + <bitfield name="TIMING_0" pos="31" type="boolean"/> </reg32> <reg32 offset="0x01C" name="START"/> <reg32 offset="0x020" name="PACK_3D"/> -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
