In the last mail Philip Blundell said:
Richard Atterer wrote:
> >Hm, but conditional execution of SWIs isn't possible with this system.
> >The extra branch would affect both performance and code density.
>
> Well, in practice SWIs are almost never conditional anyway - you normally
> decide whether or not you are going to do the syscall before you start
> marshalling arguments and so on. The only exception that comes to mind is
> breakpoints; offhand I can't think of an efficient way to make them work.
Having written ARM assembler to talk to RISC OS I can see good reason to use
conditional SWIs - mostly common would be a string of SWIs you don't expect
to fail with all bar the first VC, to save 1 VS instruction per SWI to branch
or return the error case.
However, RISC OS SWI calls
(1) appear to be designed for an assembly language (rather than C) interface
(2) (almost) all return VS to signal errors
(3) sometimes take arguments direct from one SWI call into the next
I've never programmed in assembler for ARM based Unix, so don't know what the
calling interface is like, but would suspect that the three conditions above
are all not met, hence the opportunities to usefully use conditional SWI calls
would be much less on ARM unix.
[You can see how the later RISC OS SWIs appear to be designed more for a C
interface - they always return a result in R0, even if the next SWI you
logically call has that value in R1. (DDEUtils long CLI calls, IIRC)(contrast
with WIMP SWI calls, if you're interested]
Nick
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