Dear Ward,
Thanks for your reply. What I am doing is to write a general bootloader for
both WinCE and ARM Linux, and use either serial or USB as console channels.
The bootloader is based on polling.
Now the USB interrupt sources seem work, but I met a strange phenomenon.
The EP0 FIFO can only send the first packet (8-Bytes) corresponding to
standard device descriptor request.
After the first packet has been sent (and ACK'ed, as OPR,IPR and SE are all
not set for the next EP0 IRQ), the write count register doesn't change with
the next writing of byte, so the sending process is hanged. Then the host
tried to reset the UDC, and do the sending again, but still fail.
The code is almost the same as in linux/arch/arm/mach-sa1100/Usb_ep0.c that
tried to read the write count register several times to solve the problem.
Is this a specific hardware or just a timing problem ?
Paul Wang.
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