On Sat, Sep 29, 2001 at 04:29:34PM +0200, Eric BENARD / FREE wrote:
> > hsync/vsync len is the width of the line / frame clock pulse in pixclocks /
> > lines.
> >
> ok so in my case :
You've totally misunderstood the above explaination. In the following
diagrams, _ means logic 0, ~ means logic 1, = means data present. If
you're having problems reading this diagram, switch your m$ mail reader
to use Courier New - this email is designed to be monospaced, not
proportionally spaced.
>--<a
pixclock _~_~_~_~_~_~_~_~_~_~_~_~_~_~_~_~_~_~_~_~_
data ============____________________=========
LCLK __________________~~~~~~~~~~_____________ (or HSYNC)
>------<b >----<d
>----------<c
There are 4 timings indicated in the above picture, 'a', 'b', 'c', 'd'.
'a' is the pixel clock period, pixclock.
'b' is the number of pixel clock cycles between the end of the data
for the line, and the start of the line clock (LCD speak) or H
sync (CRT speak). It is known as the "Right Margin".
'c' is the number of clock cycles that the line clock or H sync is
held active for. It is known as hsync_len.
'd' is the number of pixel clock cycles between the end of the line
clock or H sync and the start of the line data. It is known
as the "Left Margin".
Ok, lets now pretend that pixclock is actually LCLK, and LCLK is actually
FCLK, and HSYNC is VSYNC. Re-read the above explaination, and you have
the other explaination.
Hope this helps.
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