Hi,

I'm investigating on a strange probklem I have on Assabet and a SA1110 
board similar to Assabet :
- when I use bootldr, no problem, the board start well everytime I turn 
power on
- when I use redboot, big problem : 1 time out of 20, the board starts 
properly. The other times it does nothing. I assume this is not a 
hardware problem as bootldr runs fine.

I've run arm-elf-objdump -D on both files and what I get is at the end 
of this mail.

My question : in the redboot dump, are the exception handlers properly 
mapped and is their content good ?
This doesn't look very clear to me and the content of 
.undefined_instruction, .softwxare_interrupt, .abort_prefetch, 
.abort_data, .IRQ & .FIq seems strange to me compared to what is in 
bootldr and which seems more logical to me.

Many thanks

Eric

*********** redboot :
50000000 <__exception_handlers>:
50000000:       e59ff018        ldr     pc, [pc, #18]   ; 50000020 <vectors>
50000004:       e59ff018        ldr     pc, [pc, #18]   ; 50000024 
<.undefined_instruction>
50000008:       e59ff018        ldr     pc, [pc, #18]   ; 50000028 
<.software_interrupt>
5000000c:       e59ff018        ldr     pc, [pc, #18]   ; 5000002c 
<.abort_prefetch>
50000010:       e59ff018        ldr     pc, [pc, #18]   ; 50000030 
<.abort_data>
50000014:       00000000        andeq   r0, r0, r0
50000018:       e59ff018        ldr     pc, [pc, #18]   ; 50000038 <.IRQ>
5000001c:       e59ff018        ldr     pc, [pc, #18]   ; 5000003c <.FIQ>

50000020 <vectors>:
50000020:       00000060        andeq   r0, r0, r0, rrx

50000024 <.undefined_instruction>:
50000024:       5000037c        andpl   r0, r0, ip, ror r3

50000028 <.software_interrupt>:
50000028:       50000400        andpl   r0, r0, r0, lsl #8

5000002c <.abort_prefetch>:
5000002c:       50000438        andpl   r0, r0, r8, lsr r4

50000030 <.abort_data>:
50000030:       500004b4        strplh  r0, [r0], -r4
50000034:       00000000        andeq   r0, r0, r0

50000038 <.IRQ>:
50000038:       500005bc        strplh  r0, [r0], -ip

5000003c <.FIQ>:
5000003c:       50000584        andpl   r0, r0, r4, lsl #11
Disassembly of section .text:

50000040 <reset_vector>:
50000040:       e3a01412        mov     r1, #301989888  ; 0x12000000
50000044:       e59f26c8        ldr     r2, [pc, #6c8]  ; 50000714 
<_eCos_id+0x14>
50000048:       e3822a02        orr     r2, r2, #8192   ; 0x2000
5000004c:       e3822901        orr     r2, r2, #16384  ; 0x4000
50000050:       e5812000        str     r2, [r1]


************ bootldr :
00000000 <ResetEntryPoint>:
        0:       ea000095        b       25c <HiReset>

00000004 <UndefEntryPoint>:
        4:       ea00000b        b       38 <HandleUndef>

00000008 <SWIEntryPoint>:
        8:       ea00001b        b       7c <HandleSWI>

0000000c <PrefetchAbortEntryPoint>:
        c:       ea00002b        b       c0 <HandlePrefetchAbort>

00000010 <DataAbortEntryPoint>:
       10:       ea00004b        b       144 <HandleDataAbort>

00000014 <NotUsedEntryPoint>:
       14:       ea000078        b       1fc <HandleNotUsed>

00000018 <IRQEntryPoint>:
       18:       ea00005a        b       188 <HandleIRQ>

0000001c <FIQEntryPoint>:
       1c:       ea000068        b       1c4 <HandleFIQ>
       20:       646c7462        strvsbt r7, [r12], -#1122
       24:       00020e0f        andeq   r0, r2, pc, lsl #28
       28:       00000000        andeq   r0, r0, r0
       2c:       01030004        tsteq   r3, r4
       30:       00000007        andeq   r0, r0, r7
       34:       54425341        strplb  r5, [r2], -#833



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