ARM instruction timing question

[christophe leroy]

In case I have something like

ldr r6,[r7]
xor r3,r4,r3
xor r1,r2,r1
xor r2,r3,r2
xor r6,r6,r2

If [r7] value isn't in cache, will the processeur stall until it get it
from memory, or will
it execute the three following instructions while loading the r6 value
from memory ?

christophe

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