On Tue, Oct 19, 1999, Francois Desloges <[EMAIL PROTECTED]> wrote:
>Definitely :-)
>But I now doubt that it has anything to do with the NIC card.
>I'm trying to get some feedback from the Russel's BIOS I've downloaded
in Bank
>#3 of my EBSA-285 with a JTAG utility from Intel (binary only :-().
>
>Built as an 1.05 ELF bios with
>TEXTADDR = 0x410c00c0
>and -DDEBUG tailed to the definiton of CFLAGS in the Makefile
I use TEXTADDR = 0x41000080
(the AIF header is 128 bytes)
>The POST test from ARM, downloaded in any of the banks with the same JTAG
>utility, works perfectly. And generate fabulous printf on the terminal.
>
>With the BIOS, we don't even get at the point where we can read the first
>>printf("EBSA285 Linux BIOS v"VERSION" (c) 1998-1999 Russell King
>>([EMAIL PROTECTED])\n\n");
>in start_main.
>Not even the little custom printf we've added on the first line of start_main
>get outputed to terminal.
>
>Sometimes, the bios resulting from mkaif bios.elf is smaller than bios.elf
>itself, sometimes it is bigger. Without any pods on the EBSA to plug a logic
>analyser on, I wonder how we can understand what is happening...
It's possible that there is a bug in the ELF version of mkaif since I
made it ;)
I'll try to upload the version I use here (I beleive it's the same as the
one in Russel's 1.05 version, but I'm not sure I didn't change anything
so I'll double check, ping me if you don't hear from me by Friday).
One thing you can do for debugging is to add some serial output in the
assembly entry code (crt0.S). I had to make some changes to the RAM
detection code for it to work on my board, but I can't tell now if the
failure of Russel code was due to a change in the 285, or tue a HW bug we
had with RAM which was fixed in our latest prototype.
Anyway, here's my version of the code (the beginning of crt0.S, I didn't
copy the whole file, all the rest didn't change). Notice the debugging
serial output (yes, I know, I could have used strings ;)
#include "bios/linkage.h"
#include "bios/config.h"
#define CSR_BASE 0x42000000
#define SDRAM_TIMING 0x10c
#define SDRAM_ADDR_SZ0 0x110
#define SDRAM_ADDR_SZ1 0x114
#define SDRAM_ADDR_SZ2 0x118
#define SDRAM_ADDR_SZ3 0x11c
#define SDRAM_BASE 0x40000000
#define SDRAM_NRARRAYS 4
#define SDRAM_ARRAYOFF 0x00004000
#define FLUSH_BASE SDRAM_BASE
#define XBUS_CYCLE 0x148
#define XBUS_STROBE 0x14C
#define SA_CONTROL 0x13C
#define UARTDR 0x160
#define BAUD_RATE_DIVISOR 19/*40*/
#define MAX_AREA_SIZE 32768
#define SDRAM_BURST_LEN 2 /* Burst size is 4 */
#define SDRAM_BURST_TYPE 0 /* Linear burst */
#define SDRAM_CAS_LAT 2 /* CAS latency (2 or 3 supported) */
#define SDRAM_RASTOCAS_LAT 2 /* RAS-to-CAS latency (2 or 3 supported) */
#define SDRAM_MODE ((SDRAM_BURST_LEN<<2)|(SDRAM_BURST_TYPE<<5)| \
(SDRAM_CAS_LAT<<6))
/* Init values for XBus */
#if 0
#define INIT_XBUS_CYCLE 0x000016DB /* 0001-011 0-11 01-1 011 */
#define INIT_XBUS_STROBE 0xfcfcfcfc /* fc: __-- (1100) */
#else
#define INIT_XBUS_CYCLE 0x00003FFF /* 0011-111 1-11 11-1 111 */
#define INIT_XBUS_STROBE 0xe3e3e3e3 /* fc: --___-- (1110 0011) */
#endif
#define XCS_2 0x40000000
#define XCS_1 0x20000000
#define XCS_0 0x10000000
#define XBUS_INIT (XCS_2 | XCS_1 | XCS_0)
#define SA_CTL_INIT (XBUS_INIT | ROM_SETUP)
#define ROM_TIMING 0x0fff0000
#define ROM_SETUP 0x00000000 /* Everything 16 cycles */
#define XBUS_0_BASE 0x40010000
#define XBUS_1_BASE 0x40011000
#define XBUS_2_BASE 0x40012000
.text
@ Entry
.globl _entry
_entry:
bic r11, lr, #3
mrs r0, cpsr
bic r0, r0, #0x1f
orr r0, r0, #0xd3
msr cpsr, r0
ldr sp, [r11, #8]
/*
* switch the ROM memory map
* so that we can access the SDRAM
*/
ldr pc, 1f
1: .word switch
switch:
mov r0, #0
mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 @ flush all caches
mrc p15, 0, r0, c1, c0 @ Control reg
bic r0, r0, #0x0d @ D-cache, wback & MMU off
bic r0, r0, #1 << 12 @ I-cache off
mcr p15, 0, r0, c1, c0 @ Control reg
#ifdef CONFIG_INIT_XBUS
/* Init X-Bus */
mov r0, #CSR_BASE
ldr r1, =SA_CTL_INIT
str r1, [r0, #SA_CONTROL]
ldr r1, =INIT_XBUS_CYCLE
str r1, [r0, #XBUS_CYCLE]
ldr r1, =INIT_XBUS_STROBE
str r1, [r0, #XBUS_STROBE]
/* Set leds to OFF */
ldr r0, =XBUS_1_BASE
mov r1, #0xff
str r1, [r0]
#endif
/* Init serial */
bl ser_init
mov r0, #'H'
bl ser_printc
mov r0, #'E'
bl ser_printc
mov r0, #'L'
bl ser_printc
mov r0, #'L'
bl ser_printc
mov r0, #'O'
bl ser_printc
mov r0, #10
bl ser_printc
/*
* Initialise SDRAM. This copes with the SDRAM in any state -
* it does a complete initialisation and allocation of all
* banks.
*
* Turn off SDRAM refresh
*/
mov r0, #0
mov ip, #CSR_BASE
str r0, [ip, #SDRAM_TIMING]
/*
* Wait for any refresh cycles to complete
*/
mov r0, #64
1: subs r0, r0, #1
bgt 1b
/*
* All-banks precharge SDRAM arrays
*/
mov r0, #SDRAM_BASE
mov r1, #SDRAM_NRARRAYS
1: ldr r2, [r0]
ldr r2, [r0]
add r0, r0, #SDRAM_ARRAYOFF
subs r1, r1, #1
bgt 1b
/*
* Write mode registers
*/
mov r0, #SDRAM_BASE
orr r0, r0, #SDRAM_MODE/*#0x84*//*#0x88*/ @ Tcas
mov r1, #SDRAM_NRARRAYS
1: str r0, [r0]
add r0, r0, #SDRAM_ARRAYOFF
subs r1, r1, #1
bgt 1b
/*
* Turn on minimum SDRAM refresh
*/
mov r0, #0x00010000
orr r0, r0, #0x00000b00
orr r0, r0, #(0x00000005|(SDRAM_CAS_LAT<<6)|(SDRAM_RASTOCAS_LAT<<4))
str r0, [ip, #SDRAM_TIMING]
/*
* Set size to maximum
*/
mov r1, #SDRAM_NRARRAYS
add r2, ip, #SDRAM_ADDR_SZ0
mov r0, #0x2f /* We begin with mode 2 ! */
1: str r0, [r2], #4
add r0, r0, #64*1024*1024
subs r1, r1, #1
bgt 1b
/*
* Wait for banks to be refreshed
*/
mov r0, #10
mov r1, #0
1: subs r1, r1, #2
bgt 1b
subs r0, r0, #1
bgt 1b
/*
* Set SDRAM refresh to normal
*/
mov r0, #0x001a0000
orr r0, r0, #0x00000b00
orr r0, r0, #0x000000a5
str r0, [ip, #SDRAM_TIMING]
mov r4, #0x00000000
1: mov r5, #0
/*
* Detect RAM multiplexer settings
*/
mov r0, #10
bl ser_printc
mov r0, #'R'
bl ser_printc
mov r0, #'4'
bl ser_printc
mov r0, #':'
bl ser_printc
mov r0, r4
bl ser_printhex
mov r0, r4 @ check for presence
add r1, r4, #64
bl testram
bne 4f
mov r0, #'P'
bl ser_printc
/* Check for mode 0 if aliased on 21 */
mov r0, r4 @ check bit 21
orr r1, r0, #1 << 21
bl testram
orreq r5, r5, #8
moveq r0, #'N'
movne r0, #'A'
bl ser_printc
/* Check for mode 2 if !aliased on bit 23 */
mov r0, r4 @ check bit 23
orr r1, r0, #1 << 23
bl testram
orrne r5, r5, #4
moveq r0, #'N'
movne r0, #'A'
bl ser_printc
/* Check for mode 4 if !aliased on bit 22 */
mov r0, r4 @ check bit 22
orr r1, r0, #1 << 22
bl testram
orrne r5, r5, #2
moveq r0, #'N'
movne r0, #'A'
bl ser_printc
/* Now catch most mode 1 via bit 24 */
mov r0, r4 @ check bit 24
orr r1, r0, #1 << 24
bl testram
orrne r5, r5, #1
moveq r0, #'N'
movne r0, #'A'
bl ser_printc
adr r1, ram_modes @ convert test -> mux
ldrb r6, [r1, r5]
mov r0, #'M'
bl ser_printc
mov r0, r6
bl ser_printhex
orr r6, r6, r4
add r0, ip, #SDRAM_ADDR_SZ0 @ set mux correctly
orr r5, r6, #7 @ leave size at 64MB
str r5, [r0, r4, lsr #24]
/*
* Detect RAM array size
*/
mov r5, #1 << 20
mov r7, #0
2: add r0, r4, r5
add r1, r4, r5, lsr #1
bl testram
bne 3f
mov r5, r5, lsl #1
cmp r7, #7
addne r7, r7, #1
bne 2b
3: orr r5, r6, r7
mov r0, #'S'
bl ser_printc
mov r0, r7
bl ser_printhex
4: add r0, ip, #SDRAM_ADDR_SZ0
str r5, [r0, r4, lsr #24] @ set array size
add r4, r4, #0x04000000
teq r4, #0x10000000
bne 1b
mov r0, #10
bl ser_printc
/*
* Allocate RAM addresses
*/
mov r3, #7 @ start at largest size
mov r4, #0x00000000
1: mov r5, #SDRAM_NRARRAYS
add r2, ip, #SDRAM_ADDR_SZ0
2: ldr r0, [r2], #4 @ Read SDRAM size & addr
and r1, r0, #7
teq r1, r3
bne 3f
and r0, r0, #127 @ Preserve size etc
orr r0, r0, r4 @ Add base address
str r0, [r2, #-4] @ Write SDRAM size & addr
mov r0, #524288
add r4, r4, r0, lsl r1 @ Next address
3: subs r5, r5, #1
bgt 2b
subs r3, r3, #1
bgt 1b
/* Print out detected amount of RAM */
mov r0, #'R'
bl ser_printc
mov r0, #'A'
bl ser_printc
mov r0, #'M'
bl ser_printc
mov r0, #':'
bl ser_printc
mov r0, r4
bl ser_printhex
mov r0, #10
bl ser_printc
mrc p15, 0, r0, c1, c0 @ Control reg
bic r0, r0, #0x0d @ D-cache, wback & MMU off
orr r0, r0, #1 << 12 @ I-cache on
mcr p15, 0, r0, c1, c0 @ Control reg
mov r0, #'C'
bl ser_printc
/* At this point, sp contains the size of the datas. Those
are copied to RAM address 0x1000 */
mov r1, #0x1000
ldr r2, =SYMBOL_NAME(_etext)
1: ldr r0, [r2], #4
str r0, [r1], #4
subs sp, sp, #4
bgt 1b
mov r0, #'D'
bl ser_printc
/* BSS is initialized */
mov r0, #0
ldr r1, =SYMBOL_NAME(_bss_start)
ldr r2, =SYMBOL_NAME(_end)
1: str r0, [r1], #4
cmp r1, r2
blt 1b
mov r0, #'B'
bl ser_printc
/* Set stack to top of RAM -1Mb */
sub sp, r4, #1048576
bl vec_init
ldr r0, =SYMBOL_NAME(ram_size)
str r4, [r0]
mov r0, #'J'
bl ser_printc
bl SYMBOL_NAME(start_main)
l: b l
ram_modes:
.byte 0x00
.byte 0x00
.byte 0x00
.byte 0x00
.byte 0x00
.byte 0x00
.byte 0x00
.byte 0x00
.byte 0x20
.byte 0x20
.byte 0x20
.byte 0x20
.byte 0x40
.byte 0x40
.byte 0x10
.byte 0x30
.align 4
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