On Wed, 12 Jan 2000 17:11:30 -0500, Paul Koning wrote:
>>>>>> "Erik" == Erik Mouw <[EMAIL PROTECTED]> writes:
>
> Erik> On Wed, 12 Jan 2000 16:17:16 +1100 (EST), Adam 'WeirdArms'
> Erik> Wiggins wrote:
> >> Does the arm port of binutils as do ANY instruction reordering for
> >> load delay slots on the StrongARM SA-1 core or any others?
>
> Erik> Not that I know; it is certainly not the task of an assembler
> Erik> to reorder instructions.
>
> That's the usual state of affairs but it isn't always true.
>
> I think GAS does do it for MIPS. Certainly GCC puts out directives to
> the assembler that sound like they are turning reordering on and off.
> Perhaps it is for non-gas assemblers?
Hmm, that means that there is a risk that if the gcc folks come up with a
smart optimizer for better performance, the assember could ruin the
performance by using its dumber optimizer.
I just found out that the SGI IRIX6 assembler also has an optimize switch,
and it is used by gcc (2.95.2). However, I can't find an optimize switch
in the GAS documentation, I think you mixed up the two assemblers.
> Also, the DEC Alpha assembler (VMS one, at least) has an "optimize"
> switch. :-) It can do that because it uses the same back end as the
> compilers.
The IRIX6 assembler just reschedules the code, I think the Alpha
assembler does the same. There's nothing more it can do: global
optimizations like dead code removal is (or should be) already done by the
compiler..
Erik
--
LART. 250 MIPS under one Watt.
http://www-ict.its.tudelft.nl/~erik/open-source/LART/
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