> I'm using an uncompressed Image and loading to C0008000.
>
> > Another possibility: If the Icache has not been enabled up
> to now, turning
> > on the buffers and the Icache initiates an 8 word burst
> transfer on the
> > memory buss. If the memory timing is not set correctly,
> especially when
> > using SDRAMs on the SA1110, or there are other signal
> integrity issues, this
> > is a good time for things to blow up. How do I know this???
>
> Is it possible to test for this by NOT enabling the
> Icache at this
> point in head-armv.S? Or will that blow up for other reasons?
>
> Thanks,
> Chris
Try inserting some debug code: Turn the Icache on without turning on the mmu
or enabling the buffers and see if you can still get output. Then try
turning on the MMU but do not enable write buffer and Dcache*. If you can't
survive turning on just the Icache with MMU off then don't waste time
fooling around with the MMU code because it's most likely you have a
hardware problem, or a software inspired hardware problem (bad hardware
setup in your bootloader).
//Jeff
*Consult the SA1110 manual or other suitable reference for legal
combinations of write buffer, data cache, and MMU bits (hint: there aren't
many...)
unsubscribe: body of `unsubscribe linux-arm' to [EMAIL PROTECTED]
++ Please use [EMAIL PROTECTED] for ++
++ kernel-related discussions. ++
