I'm seeking to write some kind of high-level RISC OS emulation layer for Linux (and potentially NetBSD), akin to what iBCS2/ROSE do at the moment. A further addendum to the project would be an instruction-level emulation core which would run on non-ARM architectures, where 26-bit ARM code can't be executed natively within the control of the kernel; ideally the majority of code could be executed speedily, being mainly SWI calls to high-level emulations, and thus make a number of RISC OS applications usable. There are a number of issues to consider; I have a draft list of ideas. I'm going to start a mailing list: can anyone think of a better name for the project than `rose'? If anyone's interested in this on any (developer) level, please just drop me a brief note. c. unsubscribe: body of `unsubscribe linux-arm' to [EMAIL PROTECTED] ++ Please use [EMAIL PROTECTED] for ++ ++ kernel-related discussions. ++
