Christian
> Interesting point, give me a moment to check that. That finally makes
> all the hardware I have standing around here valuable :)
Yes. At the very least it provides an initial standards based path for P2P DMAs
across RPs which is something we have discussed on this list in the past as
being desirable.
BTW I am trying to understand how an ATS capable EP function determines when to
perform an ATS Translation Request (ATS TR). Is there an upstream example of
the driver for your APU that uses ATS? If so, can you provide a pointer to it.
Do you provide some type of entry in the submission queues for commands going
to the APU to indicate if the address associated with a specific command should
be translated using ATS or not? Or do you simply enable ATS and then all
addresses passed to your APU that miss the local cache result in a ATS TR?
Your feedback would be useful and I initiate discussions within the NVMe
community on where we might go with ATS...
Thanks
Stephen
