On Mon, 07 Oct 2024 18:16:18 -0500
Ira Weiny <ira.we...@intel.com> wrote:
> Additional DCD region (partition) information is contained in the DSMAS
> CDAT tables, including performance, read only, and shareable attributes.
>
> Match DCD partitions with DSMAS tables and store the meta data.
>
> To: Robert Moore <robert.mo...@intel.com>
> To: Rafael J. Wysocki <rafael.j.wyso...@intel.com>
> To: Len Brown <l...@kernel.org>
> Cc: linux-a...@vger.kernel.org
> Cc: acpica-de...@lists.linux.dev
> Signed-off-by: Ira Weiny <ira.we...@intel.com>
One trivial comment from me.
As Rafael has raised, the ACPICA dependency in here is
going to be the blocker :(
Reviewed-by: Jonathan Cameron <jonathan.came...@huawei.com>
> +static void update_dcd_perf(struct cxl_dev_state *cxlds,
> + struct dsmas_entry *dent)
> +{
> + struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds);
> + struct device *dev = cxlds->dev;
> +
> + for (int i = 0; i < mds->nr_dc_region; i++) {
> + /* CXL defines a u32 handle while cdat defines u8, ignore upper
> bits */
CDAT
> + u8 dc_handle = mds->dc_region[i].dsmad_handle & 0xff;
> +
> + if (resource_size(&cxlds->dc_res[i])) {
> + struct range dc_range = {
> + .start = cxlds->dc_res[i].start,
> + .end = cxlds->dc_res[i].end,
> + };
> +
> + if (range_contains(&dent->dpa_range, &dc_range)) {
> + if (dent->handle != dc_handle)
> + dev_warn(dev, "DC Region/DSMAS
> mis-matched handle/range; region %pra (%u); dsmas %pra (%u)\n"
> + " setting DC region
> attributes regardless\n",
> + &dent->dpa_range, dent->handle,
> + &dc_range, dc_handle);
> +
> + mds->dc_region[i].shareable = dent->shareable;
> + mds->dc_region[i].read_only = dent->read_only;
> + update_perf_entry(dev, dent, &mds->dc_perf[i]);
> + }
> + }
> + }
> +}
