On Mon, Oct 19, 2015 at 4:08 PM, Maxime Ripard <maxime.rip...@free-electrons.com> wrote: > The PLL2 on the A10 and later SoCs is the clock used for all the audio > related operations. > > This clock has a somewhat complex output tree, with three outputs (2X, 4X > and 8X) with a fixed divider from the base clock, and an output (1X) with a > post divider. > > However, we can simplify things since the 1X divider can be fixed, and we > end up by having a base clock not exposed to any device (or at least > directly, since the 4X output doesn't have any divider), and 4 fixed > divider clocks that will be exposed. > > This clock seems to have been introduced, at least in this form, in the > revision B of the A10, but we don't have any information on the clock used > on the revision A. > > Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <w...@csie.org> -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
