On 26-02-13 23:06:51, Dmitry Baryshkov wrote: > On Tue, Jan 20, 2026 at 04:52:43PM +0200, Abel Vesa wrote: > > On 26-01-20 16:49:26, Abel Vesa wrote: > > > On 26-01-12 14:53:18, Luca Weiss wrote: > > > > Add the nodes for the UFS PHY and UFS host controller, along with the > > > > ICE used for UFS. > > > > > > > > Reviewed-by: Konrad Dybcio <[email protected]> > > > > Reviewed-by: Dmitry Baryshkov <[email protected]> > > > > Signed-off-by: Luca Weiss <[email protected]> > > > > --- > > > > arch/arm64/boot/dts/qcom/milos.dtsi | 129 > > > > +++++++++++++++++++++++++++++++++++- > > > > 1 file changed, 126 insertions(+), 3 deletions(-) > > > > > > > > diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi > > > > b/arch/arm64/boot/dts/qcom/milos.dtsi > > > > index e1a51d43943f..7c8a84bfaee1 100644 > > > > --- a/arch/arm64/boot/dts/qcom/milos.dtsi > > > > +++ b/arch/arm64/boot/dts/qcom/milos.dtsi > > > > @@ -1151,6 +1151,129 @@ aggre2_noc: interconnect@1700000 { > > > > qcom,bcm-voters = <&apps_bcm_voter>; > > > > }; > > > > > > > > + ufs_mem_phy: phy@1d80000 { > > > > + compatible = "qcom,milos-qmp-ufs-phy"; > > > > + reg = <0x0 0x01d80000 0x0 0x2000>; > > > > + > > > > + clocks = <&rpmhcc RPMH_CXO_CLK>, > > > > + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, > > > > + <&tcsr TCSR_UFS_CLKREF_EN>; > > > > + clock-names = "ref", > > > > + "ref_aux", > > > > + "qref"; > > > > + > > > > + resets = <&ufs_mem_hc 0>; > > > > + reset-names = "ufsphy"; > > > > + > > > > + power-domains = <&gcc UFS_MEM_PHY_GDSC>; > > > > + > > > > + #clock-cells = <1>; > > > > + #phy-cells = <0>; > > > > + > > > > + status = "disabled"; > > > > + }; > > > > + > > > > + ufs_mem_hc: ufshc@1d84000 { > > > > + compatible = "qcom,milos-ufshc", "qcom,ufshc", > > > > "jedec,ufs-2.0"; > > > > + reg = <0x0 0x01d84000 0x0 0x3000>; > > > > + > > > > + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH > > > > 0>; > > > > + > > > > + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, > > > > + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, > > > > + <&gcc GCC_UFS_PHY_AHB_CLK>, > > > > + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, > > > > + <&tcsr TCSR_UFS_PAD_CLKREF_EN>, > > > > > > Maybe I'm looking at the wrong documentation, but it doesn't seem to exist > > > such clock on Milos. It does exist on SM8650 though. So maybe the TCSR CC > > > driver is not really that much compatible between these two platforms. > > > > > > I take it that the UFS works. Maybe because the actual TCSR UFS clkref > > > is left enabled at boot? > > > > Oh, nevemind. I think I was looking at the wrong SoC. >
Sorry, my bad. Yes. There you go: Reviewed-by: Abel Vesa <[email protected]>
