Hi-- On 6/26/25 7:31 AM, Luo Jie wrote: > +Below is a simplified hardware diagram of IPQ9574 SoC which includes the PPE > engine and > +other blocks which are in the SoC but outside the PPE engine. These blocks > work together > +to enable the Ethernet for the IPQ SoC:: > +
[snip] > + | | +-------------------------+ +---------+ +---------+ > | | > + | |125/312.5M clk| (PCS0) | | (PCS1) | | (PCS2) | pcs > ops | | > + | +--------------+ UNIPHY0 | | UNIPHY1 | | UNIPHY2 > |<--------+ | > + +--------------->| | | | | | > | > + | 31.25M ref clk +-------------------------+ +---------+ +---------+ > | > + | | | | | | | > | > + | +-----------------------------------------------------+ > | > + |25/50M ref clk| +-------------------------+ +------+ +------+ | link > | > + +------------->| | QUAD PHY | | PHY4 | | PHY5 | > |---------+ > + | +-------------------------+ +------+ +------+ | > change > + | | > + | MDIO bus | > + +-----------------------------------------------------+ Does the 'M' on the clk signals on the left side mean megahertz (MHz)? I guess that it does, but it was a little confusing when I first saw it. Thanks. -- ~Randy
