Export Zilsd and Zclsd ISA extensions through hwprobe.

Signed-off-by: Pincheng Wang <[email protected]>
---
 Documentation/arch/riscv/hwprobe.rst  | 8 ++++++++
 arch/riscv/include/uapi/asm/hwprobe.h | 2 ++
 arch/riscv/kernel/sys_hwprobe.c       | 2 ++
 3 files changed, 12 insertions(+)

diff --git a/Documentation/arch/riscv/hwprobe.rst 
b/Documentation/arch/riscv/hwprobe.rst
index 2aa9be272d5d..538ab6c08f7b 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -275,6 +275,14 @@ The following keys are defined:
        ratified in commit 49f49c842ff9 ("Update to Rafified state") of
        riscv-zabha.
 
+  * :c:macro:`RISCV_HWPROBE_EXT_ZILSD`: The Zilsd extension is supported as
+       defined in the RISC-V ISA manual starting from commit 
f88abf1("Integrating
+       load/store pair for RV32 with the main manual") of the riscv-isa-manual.
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZCLSD`: The Zclsd extension is supported as
+       defined in the RISC-V ISA manual starting from commit 
f88abf1("Integrating
+       load/store pair for RV32 with the main manual") of the riscv-isa-manual.
+
 * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated.  Returns similar values 
to
      :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was
      mistakenly classified as a bitmask rather than a value.
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h 
b/arch/riscv/include/uapi/asm/hwprobe.h
index aaf6ad970499..e086179bb4fa 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -82,6 +82,8 @@ struct riscv_hwprobe {
 #define                RISCV_HWPROBE_EXT_ZAAMO         (1ULL << 56)
 #define                RISCV_HWPROBE_EXT_ZALRSC        (1ULL << 57)
 #define                RISCV_HWPROBE_EXT_ZABHA         (1ULL << 58)
+#define        RISCV_HWPROBE_EXT_ZILSD (1ULL << 59)
+#define        RISCV_HWPROBE_EXT_ZCLSD (1ULL << 60)
 #define RISCV_HWPROBE_KEY_CPUPERF_0    5
 #define                RISCV_HWPROBE_MISALIGNED_UNKNOWN        (0 << 0)
 #define                RISCV_HWPROBE_MISALIGNED_EMULATED       (1 << 0)
diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index 0b170e18a2be..12f4b68ad2ac 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -111,6 +111,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
                EXT_KEY(ZCA);
                EXT_KEY(ZCB);
                EXT_KEY(ZCMOP);
+               EXT_KEY(ZCLSD);
                EXT_KEY(ZICBOM);
                EXT_KEY(ZICBOZ);
                EXT_KEY(ZICNTR);
@@ -119,6 +120,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
                EXT_KEY(ZIHINTPAUSE);
                EXT_KEY(ZIHPM);
                EXT_KEY(ZIMOP);
+               EXT_KEY(ZILSD);
                EXT_KEY(ZKND);
                EXT_KEY(ZKNE);
                EXT_KEY(ZKNH);
-- 
2.39.5


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