On Thu, 21 Aug 2025 21:44:21 +0100,
Mark Brown <[email protected]> wrote:
>
> On Wed, Aug 20, 2025 at 11:02:11PM +0100, Marc Zyngier wrote:
> > Mark Brown <[email protected]> wrote:
>
> > > + // EL, or to GCSCR_ELx.EXLOCKEN for an exception to the same
> > > + // exception level. See ARM DDI 0487 RWTXBY, D.1.3.2 in K.a.
nit: I think you can drop the section number in the ARM ARM. The rule
"numbers" are stable across revision of the document, and K.a is
already absolutely ancient (over a year old and two revisions behind).
> > > + new |= enter_exception64_gcs(vcpu, mode, target_mode);
> > > +
> > > new |= PSR_D_BIT;
> > > new |= PSR_A_BIT;
> > > new |= PSR_I_BIT;
>
> > But that's not the only case where we have to deal with EXLOCK, is it?
> > What of ERET and its PAuth variants? R_TYTWB says:
>
> > <quote>
> > If in AArch64 state, any of the following situations can cause an
> > illegal exception return:
> >
> > [...]
> >
> > - If the Effective value of GCSCR_ELx.EXLOCKEN is 1 and PSTATE.EXLOCK
> > is 0, the execution of an exception return instruction to return to
> > the current Exception level ELx.
> > </quote>
>
> > My reading of the spec is that this needs handling.
>
> Am I right in thinking that this handling is needed for the NV case
> only?
So far, NV is indeed the only case where we have to emulate ERET.
M.
--
Without deviation from the norm, progress is not possible.
