Hi Vivian, At the time vector emulation was added in OpenSBI, I asked Nylon if it was going to be backported: https://lore.kernel.org/opensbi/cahceehj7jdhhf_c8jnghezfbjjwp+0m6gzvsphk+blmvyyd...@mail.gmail.com/
Seems like it wasn't backported :) So yeah, it definitely needs to be added to the kernel misaligned handling code. Thanks, Clément On Thu, Dec 25, 2025 at 11:14 AM Vivian Wang <[email protected]> wrote: > > Hi Clément and riscv maintainers: > > On 5/23/25 18:19, Clément Léger wrote: > > Now that the kernel can handle misaligned accesses in S-mode, request > > misaligned access exception delegation from SBI. This uses the FWFT SBI > > extension defined in SBI version 3.0. > > > > Signed-off-by: Clément Léger <[email protected]> > > Reviewed-by: Andrew Jones <[email protected]> > > --- > > arch/riscv/include/asm/cpufeature.h | 3 +- > > arch/riscv/kernel/traps_misaligned.c | 71 +++++++++++++++++++++- > > arch/riscv/kernel/unaligned_access_speed.c | 8 ++- > > 3 files changed, 77 insertions(+), 5 deletions(-) > > This causes a regression on platforms where vector misaligned access can > be emulated with OpenSBI (since OpenSBI commit c2acc5e ("lib: > sbi_misaligned_ldst: Add handling of vector load/store"), because this > disables that with FWFT. This means that vector misaligned loads and > stores that were emulated instead get a SIGBUS. > > This happens on Sophgo SG2044 and SpacemiT K1. Notably this causes these > platforms to fail Zicclsm which stipulates that misaligned vector memory > accesses succeed if vector instructions are available at all [1]. > > I'm not very certain why vector emulation support was omitted in this > series. Should we perhaps add the same emulation support to Linux as > well for the sake of these kind of platforms? > > Thanks, > Vivian "dramforever" Wang > > [1]: https://github.com/riscv/riscv-profiles/issues/58 >
