I wonder if we could get some more input on whether this is a good generally accepted practice anyway. I have a semi solution for my problems, and like for Robert it involves dropping these figures down to something more reasonable
Ed W
John Knottenbelt wrote:
Well, I notice that av7110.c (at least in the 2.6.0-test3 kernel) writes:
./ttpci/av7110.c: saa7146_write(dev, PCI_BT_V1, 0x1c00101f);
and
./ttpci/budget-core.c: saa7146_write(dev, PCI_BT_V1, 0x001c0000 |
./ttpci/budget-core.c: (saa7146_read(dev, PCI_BT_V1) & ~0x001f0000));
Assuming that budget-core write happens after av7110 then the mask is:
0x1c00101f | 0x001c0000 = 0x1c1c101f
Which I believe decodes to: FIFO Threshold 1: 32 dwords PCI Burst length 1: 128 dwords FIFO Threshold 2: 4 dwords PCI Burst length 2: 16 dwords FIFO Threshold 3: 4 dwords PCI Burst length 3: 128 dwords PCI Burst length DEBI: 128 dwords
So it appears that Budget cards are using 128 dwords for DEBI PCI Burst Length.
According to Robert's previous message 128 dwords might be too long for some chipsets?
How can we tell if the chipset can handle these parameters?
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