On Mon, Jan 19, 2009 at 7:46 AM, Jaya Kumar <jayakumar.l...@gmail.com> wrote: > On Mon, Jan 19, 2009 at 4:05 AM, Ryan Mallon <r...@bluewatersys.com> wrote: >> Jaya Kumar wrote: >>> Hi friends, >>> >> >>> + >>> + /* BATCH GPIO OUTPUT */ >>> +int gpio_set_batch(unsigned gpio, u32 values, u32 bitmask, int maskwidth); >>> + >>> +The following examples help explain how this function is to be used. >>> + Q: How to set gpio pins 0 through 7 to all 0? (8 bits) >>> + A: gpio_set_batch(gpio=0, values=0x0, bitmask=0xFF, width=8); >>> + Q: How to set gpio pins 58 through 73 to all 1? (16 bits) >>> + A: gpio_set_batch(gpio=58, values=0xFFFF, bitmask=0xFFFF, width=16); >>> + Q: How to set gpio pins 16 through 47 to 0xCAFEC001? (32 bits) >>> + A: gpio_set_batch(gpio=16, values=0xCAFEC001, bitmask=0xFFFFFFFF, >>> width=32); >>> + >> >> Can the gpio_set_batch function be used to set non-consecutive gpios? >> For example: >> >> gpio_set_batch(0, 0x0, 0x88, 8); >> >> To clear gpios 3 and 7? It looks like the pxa implementation will > > Hi Ryan, > > For the first part, yes, it can do non-consecutive gpios by using the > mask. Pins 3 and 7 are handled using a 5-bit mask. You'd do > gpio_set_batch(3 <- starting pin is gpio 3, 0x0 <- clear, 0x1F <- > mask, 5 <- bit width of mask);
Correction: I meant to write 0x11 for the mask above (instead of 0x1F) since you only want to clear the starting pin 3 and the ending pin 7 in the 5 bits. If we used 0x1F here, then we would clear all 5 bits rather than just 3 and 7. Thanks, jaya -- To unsubscribe from this list: send the line "unsubscribe linux-embedded" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
