On 9/3/25 22:47, Rob Herring wrote:
On Wed, Sep 03, 2025 at 03:29:05PM +0530, Manikanta Guntupalli wrote:
Add device tree binding documentation for the AMD I3C master controller.
Signed-off-by: Manikanta Guntupalli <[email protected]>
---
Changes for V2:
Updated commit subject and description.
Moved allOf to after required.
Removed xlnx,num-targets property.
Changes for V3:
Updated commit description.
Corrected the order of properties and removed resets property.
Added compatible to required list.
Added interrupts to example.
---
.../devicetree/bindings/i3c/xlnx,axi-i3c.yaml | 53 +++++++++++++++++++
1 file changed, 53 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i3c/xlnx,axi-i3c.yaml
diff --git a/Documentation/devicetree/bindings/i3c/xlnx,axi-i3c.yaml
b/Documentation/devicetree/bindings/i3c/xlnx,axi-i3c.yaml
new file mode 100644
index 000000000000..32f73c31121e
--- /dev/null
+++ b/Documentation/devicetree/bindings/i3c/xlnx,axi-i3c.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i3c/xlnx,axi-i3c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AMD I3C master
+
+maintainers:
+ - Manikanta Guntupalli <[email protected]>
+
+description:
+ The AXI-I3C IP is an I3C Controller with an AXI4-Lite interface, compatible
+ with the MIPI I3C Specification v1.1.1. The design includes bidirectional I/O
+ buffers that implement open collector drivers for the SDA and SCL signals.
+ External pull-up resistors are required to properly hold the bus at a Logic-1
+ level when the drivers are released.
+
+properties:
+ compatible:
+ const: xlnx,axi-i3c-1.0
Where does the version number come from? This must correspond to some
h/w documentation or it is useless.
yes it corresponds to AXI I3C Bus Interface v1.0 Product Guide (PG439)
https://docs.amd.com/r/en-US/pg439-axi-i3c
All these soft IPs are using numbering schema.
Thanks,
Michal
