Add the Thermal Management Unit (TMU) support for the Google GS101 SoC. Describe the TMU using a consolidated SoC node that includes memory resources for interrupt identification and a phandle to the ACPM IPC interface for functional control.
Define thermal zones for the little, mid, and big CPU clusters, including associated trip points and cooling-device maps to enable thermal mitigation. Signed-off-by: Tudor Ambarus <[email protected]> --- arch/arm64/boot/dts/exynos/google/gs101-tmu.dtsi | 209 +++++++++++++++++++++++ arch/arm64/boot/dts/exynos/google/gs101.dtsi | 18 ++ 2 files changed, 227 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101-tmu.dtsi b/arch/arm64/boot/dts/exynos/google/gs101-tmu.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..6262c3b890aa2f7ad572c32b30bf926df804ec1e --- /dev/null +++ b/arch/arm64/boot/dts/exynos/google/gs101-tmu.dtsi @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Google GS101 TMU configurations device tree source + * + * Copyright 2020 Samsung Electronics Co., Ltd. + * Copyright 2020 Google LLC. + * Copyright 2026 Linaro Ltd. + */ + +#include <dt-bindings/thermal/thermal.h> + +/ { + thermal-zones { + cpucl2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu_top 0>; + + trips { + big_cold: big-cold { + temperature = <20000>; + hysteresis = <5000>; + type = "active"; + }; + + big_switch_on: big-switch-on { + temperature = <70000>; + hysteresis = <2000>; + type = "active"; + }; + + big_control_temp: big-control-temp { + temperature = <90000>; + hysteresis = <5000>; + type = "passive"; + }; + + big_pre_switch_on: big-pre-switch-on { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + + big_alert2: big-alert2 { + temperature = <95000>; + hysteresis = <5000>; + type = "active"; + }; + + big_hw_throttling: big-hw-throttling { + temperature = <103000>; + hysteresis = <5000>; + type = "active"; + }; + + big_pause: big-pause { + temperature = <108000>; + hysteresis = <5000>; + type = "active"; + }; + + big_hot: big-hot { + temperature = <115000>; + hysteresis = <3000>; + type = "hot"; + }; + }; + + cooling-maps { + map0 { + trip = <&big_control_temp>; + cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpucl1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu_top 1>; + + trips { + mid_cold: mid-cold { + temperature = <20000>; + hysteresis = <5000>; + type = "active"; + }; + + mid_switch_on: mid-switch-on { + temperature = <70000>; + hysteresis = <2000>; + type = "active"; + }; + + mid_control_temp: mid-control-temp { + temperature = <90000>; + hysteresis = <5000>; + type = "passive"; + }; + + mid_pre_switch_on: mid-pre-switch-on { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + + mid_alert2: mid-alert2 { + temperature = <95000>; + hysteresis = <5000>; + type = "active"; + }; + + mid_hw_throttling: mid-hw-throttling { + temperature = <98000>; + hysteresis = <5000>; + type = "active"; + }; + + mid_pause: mid-pause { + temperature = <108000>; + hysteresis = <5000>; + type = "active"; + }; + + mid_hot: mid-hot { + temperature = <115000>; + hysteresis = <3000>; + type = "hot"; + }; + }; + + cooling-maps { + map0 { + trip = <&mid_control_temp>; + cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpucl0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu_top 2>; + + trips { + little_cold: little-cold { + temperature = <20000>; + hysteresis = <5000>; + type = "active"; + }; + + little_switch_on: little-switch-on { + temperature = <70000>; + hysteresis = <2000>; + type = "active"; + }; + + little_control_temp: little-control-temp { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + + little_pre_switch_on: little-pre-switch-on { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + + little_alert2: little-alert2 { + temperature = <100000>; + hysteresis = <5000>; + type = "active"; + }; + + little_alert5: little-alert5 { + temperature = <103000>; + hysteresis = <5000>; + type = "active"; + }; + + little_alert6: little-alert6 { + temperature = <110000>; + hysteresis = <5000>; + type = "active"; + }; + + little_hot: little-hot { + temperature = <115000>; + hysteresis = <3000>; + type = "hot"; + }; + }; + + cooling-maps { + map0 { + trip = <&little_control_temp>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + }; +}; diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index d085f9fb0f62ac2f57b104c20880e64d885d0bee..4b8c7edaddb6fd49e61496f2f21f348db0b58f10 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -74,6 +74,7 @@ cpu0: cpu@0 { compatible = "arm,cortex-a55"; reg = <0x0000>; clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; + #cooling-cells = <2>; enable-method = "psci"; cpu-idle-states = <&ananke_cpu_sleep>; capacity-dmips-mhz = <250>; @@ -86,6 +87,7 @@ cpu1: cpu@100 { compatible = "arm,cortex-a55"; reg = <0x0100>; clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; + #cooling-cells = <2>; enable-method = "psci"; cpu-idle-states = <&ananke_cpu_sleep>; capacity-dmips-mhz = <250>; @@ -98,6 +100,7 @@ cpu2: cpu@200 { compatible = "arm,cortex-a55"; reg = <0x0200>; clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; + #cooling-cells = <2>; enable-method = "psci"; cpu-idle-states = <&ananke_cpu_sleep>; capacity-dmips-mhz = <250>; @@ -110,6 +113,7 @@ cpu3: cpu@300 { compatible = "arm,cortex-a55"; reg = <0x0300>; clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; + #cooling-cells = <2>; enable-method = "psci"; cpu-idle-states = <&ananke_cpu_sleep>; capacity-dmips-mhz = <250>; @@ -122,6 +126,7 @@ cpu4: cpu@400 { compatible = "arm,cortex-a76"; reg = <0x0400>; clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL1>; + #cooling-cells = <2>; enable-method = "psci"; cpu-idle-states = <&enyo_cpu_sleep>; capacity-dmips-mhz = <620>; @@ -134,6 +139,7 @@ cpu5: cpu@500 { compatible = "arm,cortex-a76"; reg = <0x0500>; clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL1>; + #cooling-cells = <2>; enable-method = "psci"; cpu-idle-states = <&enyo_cpu_sleep>; capacity-dmips-mhz = <620>; @@ -146,6 +152,7 @@ cpu6: cpu@600 { compatible = "arm,cortex-x1"; reg = <0x0600>; clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL2>; + #cooling-cells = <2>; enable-method = "psci"; cpu-idle-states = <&hera_cpu_sleep>; capacity-dmips-mhz = <1024>; @@ -158,6 +165,7 @@ cpu7: cpu@700 { compatible = "arm,cortex-x1"; reg = <0x0700>; clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL2>; + #cooling-cells = <2>; enable-method = "psci"; cpu-idle-states = <&hera_cpu_sleep>; capacity-dmips-mhz = <1024>; @@ -639,6 +647,15 @@ watchdog_cl1: watchdog@10070000 { status = "disabled"; }; + tmu_top: thermal-sensor@100a0000 { + compatible = "google,gs101-tmu-top"; + reg = <0x100a0000 0x800>; + clocks = <&cmu_misc CLK_GOUT_MISC_TMU_TOP_PCLK>; + interrupts = <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH 0>; + samsung,acpm-ipc = <&acpm_ipc>; + #thermal-sensor-cells = <1>; + }; + trng: rng@10141400 { compatible = "google,gs101-trng", "samsung,exynos850-trng"; @@ -1861,3 +1878,4 @@ timer { }; #include "gs101-pinctrl.dtsi" +#include "gs101-tmu.dtsi" -- 2.52.0.457.g6b5491de43-goog
