Troy Kisky wrote:
> On 9/17/2010 6:09 AM, Sudhakar Rajashekhara wrote:
>> Hi,

Seems I didn't get Sudhakar's email.. I wonder why?

>> On Fri, Sep 17, 2010 at 08:32:11, Jon Povey wrote:
>>> Move the MDR load after DXR,IMR loads to avoid this race without
>>> locking.
>>
>> I remember I had some issues on OMAP-L138 with this fix, that's when
>> I reverted to configuring ICMDR before writing to DXR (Please see
>> here: https://patchwork.kernel.org/patch/75262/). I checked the BIOS
>> I2C driver code for OMAP-L138 and there also we are configuring MDR
>> before accessing DXR.

Ah :/

> How about killing the lines from commit
> c6c7c729a22bfeb8e63eafce48dbaeea20e68703
> -------------------------------
> /*
>  * First byte should be set here, not after interrupt,
>  * because transmit-data-ready interrupt can come before
>  * NACK-interrupt during sending of previous message and
>  * ICDXR may have wrong data
>  */
> if ((!(msg->flags & I2C_M_RD)) && dev->buf_len) {
>         davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++);
> dev->buf_len--; }
> ----------------------
>
> and resetting the i2c upon a NAK interrupt (after the stop)
> to clear the bad fifo data?

I can't really comment on how valid that would be and can't easily test it.

However preloading DXR does save one interrupt on transmit so the whole 
operation is faster and more efficient.

Maybe v1 of my patch, with locking, is the best option?

--
Jon Povey
jon.po...@racelogic.co.uk

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