Erratum A-006037 indicates I2C controller executes the write to I2CCR only after it sees SCL idle for 64K cycle of internal I2C controller clocks. If during this waiting period, I2C controller is disabled (I2CCR[MEN] set to 0), then the controller could end in bad state, and hang the future access to I2C register.
The mpc_i2c_fixup() function tries to recover the bus from a stalled state where the 9th clock pulse wasn't generated. However, this workaround disables and enables I2C controller without meeting waiting requirement of this erratum. This erratum applies to some 85xx SoCs. It is safe to apply to all of them for mpc_i2c_fixup(). Signed-off-by: York Sun <york...@freescale.com> --- Change log: v2: remote reviewed-by and tested-by lines added by gerrit send to proper mailing list drivers/i2c/busses/i2c-mpc.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c index b80c768..55dce43 100644 --- a/drivers/i2c/busses/i2c-mpc.c +++ b/drivers/i2c/busses/i2c-mpc.c @@ -106,7 +106,12 @@ static irqreturn_t mpc_i2c_isr(int irq, void *dev_id) static void mpc_i2c_fixup(struct mpc_i2c *i2c) { int k; - u32 delay_val = 1000000 / i2c->real_clk + 1; + u32 delay_val; +#ifdef CONFIG_PPC_85xx + delay_val = 65536 / (fsl_get_sys_freq() / 2000000); /* 64K cycle */ +#else + delay_val = 1000000 / i2c->real_clk + 1; +#endif if (delay_val < 2) delay_val = 2; @@ -116,7 +121,11 @@ static void mpc_i2c_fixup(struct mpc_i2c *i2c) writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN); udelay(delay_val); writeccr(i2c, CCR_MEN); +#ifdef CONFIG_PPC_85xx + udelay(delay_val); +#else udelay(delay_val << 1); +#endif } } -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-i2c" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html