On Thu, Jun 11, 2015 at 11:35:26AM +0200, Alexander Sverdlin wrote: > There are several cases where current clock configuration algorithm produces > not optimal results: > - truncation in "clk" calculation leads to the fact that actual BUS frequency > will be always higher than spec except two exact module frequences 8MHz and > 12MHz in the whole 7-12MHz range of permitted frequences > - driver configures SCL HIGH to LOW ratio always 1 to 1 and this doesn't work > well in 400kHz case, namely minimum time of LOW state (according to I2C Spec > 2.1) 1.3us will not be fulfilled. HIGH to LOW ratio 1 to 2 would be more > approriate here. > > Signed-off-by: Michael Lawnick <[email protected]> > Signed-off-by: Alexander Sverdlin <[email protected]>
Applied to for-next, thanks!
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