Tejun Heo wrote:
And without interrupt pending bit, shared interrupt means a lot of
spurious interrupts making it impossible to know when to expect interrupts.
IDE driver deals with this by having only one command active per
interrupt, but SATA doesn't have such scheme yet. And I don't know if
such a scheme is desirable at all.
I'm not sure which part of the IDE driver this refers to,
but there is/was code in there from 1994 or so, which enabled
sharing a single IRQ among multiple ISA IDE interfaces using
edge-triggered interrupts (rather than level-triggered).
That particular code did indeed only permit one command active per
interrupt, but only for that situation. But later on, when simplex
DMA host controllers appeared, the scheme got reorganized into
"hardware groups" (hwgroups), which were collections of IDE interfaces
which required mutual exclusion among themselves.
If only the hardware were as simple and as well documented back then
as it is (mostly) today!
Cheers
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