On 2/21/07, Alan <[EMAIL PROTECTED]> wrote:
On Wed, 21 Feb 2007 15:56:28 -0700
"Fajun Chen" <[EMAIL PROTECTED]> wrote:
> Hi Folks,
>
> I've noticed the following code in both pata_sil680.c and IDE code siimage.c
> /* FIXME: double check */
> pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255);
> I was unable to find the recommended setting in Sil680 document. Could
> someone explain the rational behind the code above? Does it need to be
> adjusted on different processors for PCI read/write performance?
The code is inherited from the original bits by Andre Hedrick who had
access to the chip errata documents, which afaik have never been
published.
Thanks for the update, Alan.
I did another experiments by changing Cache Line Size to 0x02 and
Latency Timer to 0x40 and the performance of PCI Read (Read DMA) has
been almost doubled. So this seems there may be room for further
performance enhancement by tweaking PCI configuration. One concern
about the latency timer change is increased bus hold time, could this
delay other applications which shares the PCI bus?
Since Sil3124 has better PCI read/write performance, as a reference,
could someone explain or point me to the PCI configuration code for
Sil3124? I couldn't find it in sata_sil24.c.
The kernel version used is 2.6.18-rc2 and libata version is 2.00.
Thanks,
Fajun
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