MMIO has always been like this (libata-core.c):
/* software reset. causes dev0 to be selected */
iowrite8(ap->ctl, ioaddr->ctl_addr);
udelay(20); /* FIXME: flush */
iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
udelay(20); /* FIXME: flush */
iowrite8(ap->ctl, ioaddr->ctl_addr);
The problem is mainly in finding registers you can read without side
effects or confusing the controller which might also be doing in-silicon
reset procedures.
The above is not correct per PCI posting, hence the FIXME, but it works
so far for all tested cases.
The timing is irrelevant for SATA (this merely triggers a FIS to be
sent). Most of PATA is not MMIO, so this problem is avoided. Thus the
potential affected cases are PATA MMIO, which is largely PDC and SiI, IIRC.
Ben's patch got merged because it does not change the status quo. This
warrants looking at -- its a core problem as shown above -- but it
requires thinking and testing on a problematic platform :) Maybe we can
read a PCI config register or innocuous vendor-specific register, for
the flush, on the few cases where it matters.
Jeff
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